| /external/v8/src/compiler/mips64/ |
| D | instruction-scheduler-mips64.cc | 405 TRUNC_L_S = 4, enumerator
1095 int latency = Latency::TRUNC_L_S + Latency::DMFC1; in TruncLSLatency()
1113 4 * Latency::BRANCH + Latency::SUB_S + 2 * Latency::TRUNC_L_S + in TruncUlSLatency()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 293 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,
635 (TRUNC_L_S FGR32Opnd:$src)>, FGR_64;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 403 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,
899 (TRUNC_L_S FGR32Opnd:$src)>, ISA_MIPS2, FGR_64;
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| /external/v8/src/compiler/mips/ |
| D | instruction-scheduler-mips.cc | 372 TRUNC_L_S = 4, enumerator
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| /external/v8/src/mips/ |
| D | constants-mips.h | 609 TRUNC_L_S = ((1U << 3) + 1), enumerator
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| D | assembler-mips.cc | 2974 GenInstrRegister(COP1, S, f0, fs, fd, TRUNC_L_S); in trunc_l_s()
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| D | simulator-mips.cc | 3417 case TRUNC_L_S: { // Mips32r2 instruction. in DecodeTypeRegisterSRsType()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 640 TRUNC_L_S = ((1U << 3) + 1), enumerator
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| D | assembler-mips64.cc | 3361 GenInstrRegister(COP1, S, f0, fs, fd, TRUNC_L_S); in trunc_l_s()
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| D | simulator-mips64.cc | 2844 case TRUNC_L_S: { // Mips64r2 instruction. in DecodeTypeRegisterSRsType()
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1694 22729U, // TRUNC_L_S
3408 0U, // TRUNC_L_S
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| D | MipsGenDisassemblerTables.inc | 4238 /* 667 */ MCD_OPC_Decode, 141, 13, 75, // Opcode: TRUNC_L_S
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCCodeEmitter.inc | 2599 UINT64_C(1174405129), // TRUNC_L_S
3191 case Mips::TRUNC_L_S:
10325 …64bit | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // TRUNC_L_S = 2586
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| D | MipsGenAsmWriter.inc | 3814 23500U, // TRUNC_L_S
6445 0U, // TRUNC_L_S
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| D | MipsGenFastISel.inc | 1030 return fastEmitInst_r(Mips::TRUNC_L_S, &Mips::FGR64RegClass, Op0, Op0IsKill);
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| D | MipsGenInstrInfo.inc | 2601 TRUNC_L_S = 2586,
6646 …, 1, 4, 611, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #2586 = TRUNC_L_S
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| D | MipsGenDisassemblerTables.inc | 7131 /* 339 */ MCD::OPC_Decode, 154, 20, 209, 1, // Opcode: TRUNC_L_S
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| D | MipsGenAsmMatcher.inc | 7602 …{ 9417 /* trunc.l.s */, Mips::TRUNC_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEn…
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| D | MipsGenDAGISel.inc | 28198 /* 52984*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::TRUNC_L_S), 0,
28201 // Dst: (TRUNC_L_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
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