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Searched refs:VK1 (Results 1 – 14 of 14) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td322 def maskzeroupperv1i1 : maskzeroupper<v1i1, VK1>;
335 (COPY_TO_REGCLASS VK1:$src, VK32)>;
345 (COPY_TO_REGCLASS VK1:$src, VK64)>;
360 (COPY_TO_REGCLASS VK1:$src, VK16)>;
369 (COPY_TO_REGCLASS VK1:$src, VK8)>;
409 (v1i1 VK1:$mask), (iPTR 0))),
410 (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK1:$mask, VK16),
437 (v1i1 VK1:$mask), (iPTR 0))),
438 (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK1:$mask, VK8),
487 (v1i1 VK1:$mask), (iPTR 0))),
[all …]
DX86RegisterInfo.td574 def VK1 : RegisterClass<"X86", [v1i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;}
575 def VK2 : RegisterClass<"X86", [v2i1], 16, (add VK1)> {let Size = 16;}
582 def VK1WM : RegisterClass<"X86", [v1i1], 16, (sub VK1, K0)> {let Size = 16;}
DX86InstrAVX512.td179 def v1i1_info : X86KVectorVTInfo<VK1, VK1WM, v1i1>;
2085 (outs VK1:$dst),
2896 def : Pat<(store VK1:$src, addr:$dst),
2897 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK8))>;
2900 (COPY_TO_REGCLASS (KMOVBkm addr:$src), VK1)>;
2921 defm : operation_gpr_mask_copy_lowering<VK1, v1i1>;
3028 def : Pat<(OpNode VK1:$src1, VK1:$src2),
3030 (COPY_TO_REGCLASS VK1:$src1, VK16),
3031 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
3035 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
[all …]
DX86FastISel.cpp2234 const TargetRegisterClass *VK1 = &X86::VK1RegClass; in X86FastEmitSSESelect() local
2238 unsigned CmpReg = fastEmitInst_rri(CmpOpcode, VK1, CmpLHSReg, CmpLHSIsKill, in X86FastEmitSSESelect()
/external/llvm/lib/Target/X86/
DX86InstrAVX512.td1385 (outs VK1:$dst),
2035 def : Pat<(store VK1:$src, addr:$dst),
2036 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK8))>;
2044 def : Pat<(store VK1:$src, addr:$dst),
2046 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
2073 (COPY_TO_REGCLASS (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1)), VK1)>;
2095 sub_16bit)), VK1)>;
2098 (COPY_TO_REGCLASS (i16 (EXTRACT_SUBREG $src, sub_16bit)), VK1)>;
2102 sub_16bit)), VK1)>;
2105 (COPY_TO_REGCLASS (i16 (EXTRACT_SUBREG $src, sub_16bit)), VK1)>;
[all …]
DX86RegisterInfo.td511 def VK1 : RegisterClass<"X86", [i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;}
512 def VK2 : RegisterClass<"X86", [v2i1], 16, (add VK1)> {let Size = 16;}
519 def VK1WM : RegisterClass<"X86", [i1], 16, (sub VK1, K0)> {let Size = 16;}
/external/capstone/arch/X86/
DX86GenRegisterInfo.inc697 // VK1 Register Class...
698 static MCPhysReg VK1[] = {
702 // VK1 Bit set.
1440 …{ CAPSTONE_REGISTER_CLASS("VK1"), VK1, VK1Bits, 8, sizeof(VK1Bits), X86_VK1RegClassID, 2, 2, 1, 1 …
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Duse-sgpr-multiple-times.ll227 ; GCN-DAG: v_mov_b32_e32 [[VK1:v[0-9]+]], 0x45800000
228 ; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], s[[SGPR0]], [[VS1]], [[VK1]]
/external/llvm/test/CodeGen/AMDGPU/
Duse-sgpr-multiple-times.ll231 ; GCN-DAG: v_mov_b32_e32 [[VK1:v[0-9]+]], 0x45800000
232 ; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[SGPR0]], [[VS1]], [[VK1]]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc2559 …VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] }), VK1:{ *:[v1i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v1i1…
2580 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
2593 …VK1:{ *:[v1i1] }:$src2, (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] })) => (COPY_TO_…
2614 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
2621 …VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KANDWrr:{ *:[…
2642 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
3514 …2] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
3535 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
3587 …2] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
3608 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
[all …]
DX86GenRegisterInfo.inc1330 // VK1 Register Class...
1331 const MCPhysReg VK1[] = {
1335 // VK1 Bit set.
2199 { VK1, VK1Bits, 6, 8, sizeof(VK1Bits), X86::VK1RegClassID, 2, 1, true },
4052 { 16, 16, 16, VTLists+24 }, // VK1
6687 { // VK1
7488 {1, 8}, // VK1
7594 "VK1",
7633 8, // 6: VK1
DX86GenAsmMatcher.inc4644 MCK_VK1, // register class 'VK1,VK16,VK2,VK4,VK8,VK32,VK64'
/external/honggfuzz/examples/apache-httpd/corpus_http2/
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/external/honggfuzz/examples/apache-httpd/corpus_http1/
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