| /external/llvm/lib/Target/AMDGPU/ |
| D | VIInstructions.td | 44 // VOP2 Instructions
89 // are VOP2 on SI and VOP3 on VI.
|
| D | SIInstrFormats.td | 32 field bits<1> VOP2 = 0;
68 let TSFlags{11} = VOP2;
142 let VOP2 = 1;
648 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
| D | SIDefines.h | 29 VOP2 = 1 << 11, enumerator
|
| D | SIInstrInfo.h | 256 return MI.getDesc().TSFlags & SIInstrFlags::VOP2; in isVOP2()
260 return get(Opcode).TSFlags & SIInstrFlags::VOP2; in isVOP2()
|
| D | SIInstrInfo.td | 46 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
47 // that doesn't have VOP2 encoding on VI
1141 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
1191 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1221 // VOP2 without modifiers
1786 VOP2 <op.SI, outs, ins, opName#asm, []>,
1794 VOP2 <op.VI, outs, ins, opName#asm, []>,
2072 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
2080 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
2228 // A VOP2 instruction that is VOP3-only on VI.
|
| D | SIInstructions.td | 1478 // VOP2 Instructions
2497 // VOP2 Patterns
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 40 field bit VOP2 = 0;
135 let TSFlags{8} = VOP2;
191 …let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0)…
|
| D | SIDefines.h | 34 VOP2 = 1 << 8, enumerator
|
| D | VOP2Instructions.td | 11 // VOP2 Classes
74 let VOP2 = 1;
352 // VOP2 Instructions
942 // are VOP2 on SI and VOP3 on VI.
|
| D | SIInstrInfo.h | 373 return MI.getDesc().TSFlags & SIInstrFlags::VOP2; in isVOP2()
377 return get(Opcode).TSFlags & SIInstrFlags::VOP2; in isVOP2()
|
| D | SIInstrInfo.td | 1082 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
1244 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1281 // VOP2 without modifiers
|
| D | SIInstructions.td | 691 // VOP2 Patterns
|
| /external/llvm/docs/ |
| D | AMDGPUUsage.rst | 101 VOP1, VOP2, VOP3, VOPC Instructions
107 VOP1, VOP2, and VOPC instructions based on the operands. If you want to force
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | sdwa-vop2-64bit.mir | 5 # No conversion for VOP2 instructions that have only 64-bit encoding
|
| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | AMDGPUOperandSyntax.rst | 568 VOP1/VOP2 DPP Modifiers
648 VOP1/VOP2/VOPC SDWA Modifiers
740 VOP1/VOP2/VOPC SDWA Operand Modifiers
|
| D | AMDGPUUsage.rst | 4255 For vector ALU instruction opcodes (VOP1, VOP2, VOP3, VOPC, VOP_DPP, VOP_SDWA),
4259 * _e32 for 32-bit VOP1/VOP2/VOPC
4264 VOP1/VOP2/VOP3/VOPC examples:
|
| D | AMDGPUAsmGFX7.rst | 630 VOP2 chapter
|
| D | AMDGPUAsmGFX8.rst | 777 VOP2 chapter
|
| D | AMDGPUAsmGFX9.rst | 941 VOP2 chapter
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2281 SIInstrFlags::VOP1 | SIInstrFlags::VOP2 | in validateConstantBusLimitations()
5355 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2); in cvtSdwaVOP2()
5359 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, true); in cvtSdwaVOP2b()
5386 if (BasicInstType == SIInstrFlags::VOP2 && in cvtSDWA()
5421 case SIInstrFlags::VOP2: in cvtSDWA()
|
| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2683 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2); in cvtSdwaVOP2()
2731 case SIInstrFlags::VOP2: { in cvtSDWA()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/ |
| D | sdwa_gfx9.txt | 249 # VOP2
|