| /external/jemalloc_new/include/jemalloc/internal/ |
| D | atomic_gcc_sync.h | 15 atomic_fence(atomic_memory_order_t mo) { in atomic_fence() function
67 atomic_fence(atomic_memory_order_relaxed); in atomic_pre_sc_load_fence()
69 atomic_fence(atomic_memory_order_seq_cst); in atomic_pre_sc_load_fence()
77 atomic_fence(atomic_memory_order_seq_cst); in atomic_post_sc_store_fence()
79 atomic_fence(atomic_memory_order_relaxed); in atomic_post_sc_store_fence()
98 atomic_fence(atomic_memory_order_acquire); \
107 atomic_fence(atomic_memory_order_release); \
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| D | atomic_msvc.h | 20 atomic_fence(atomic_memory_order_t mo) { in atomic_fence() function
64 atomic_fence(atomic_memory_order_acquire); \
73 atomic_fence(atomic_memory_order_release); \
77 atomic_fence(atomic_memory_order_seq_cst); \
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| D | atomic_c11.h | 15 #define atomic_fence atomic_thread_fence macro
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| D | atomic_gcc_atomic.h | 35 atomic_fence(atomic_memory_order_t mo) { in atomic_fence() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | fence-amdgiz.ll | 5 ; CHECK-LABEL: atomic_fence
11 define amdgpu_kernel void @atomic_fence() {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/XCore/ |
| D | atomic.ll | 3 ; CHECK-LABEL: atomic_fence
9 define void @atomic_fence() nounwind {
|
| /external/llvm/test/CodeGen/XCore/ |
| D | atomic.ll | 3 ; CHECK-LABEL: atomic_fence
9 define void @atomic_fence() nounwind {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrAtomics.td | 19 [(atomic_fence imm:$ordering, 0)]>, Sched<[]>;
20 def : Pat<(atomic_fence (i64 4), (imm)), (DMB (i32 0x9))>;
21 def : Pat<(atomic_fence (imm), (imm)), (DMB (i32 0xb))>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.td | 767 def : Pat<(atomic_fence (i32 4), (imm)), (FENCE 0b10, 0b11)>;
769 def : Pat<(atomic_fence (i32 5), (imm)), (FENCE 0b11, 0b1)>;
771 def : Pat<(atomic_fence (i32 6), (imm)), (FENCE_TSO)>;
773 def : Pat<(atomic_fence (i32 7), (imm)), (FENCE 0b11, 0b11)>;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrAtomics.td | 17 def : Pat<(atomic_fence (i64 4), (imm)), (DMB (i32 0x9))>;
18 def : Pat<(atomic_fence (imm), (imm)), (DMB (i32 0xb))>;
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstr64Bit.td | 501 def : Pat<(atomic_fence imm, imm), (MEMBARi 0xf)>;
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| D | SparcInstrInfo.td | 1657 // store bar for all atomic_fence in V8.
1659 def : Pat<(atomic_fence imm, imm), (STBAR)>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcInstr64Bit.td | 501 def : Pat<(atomic_fence imm, imm), (MEMBARi 0xf)>;
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| D | SparcInstrInfo.td | 1665 // store bar for all atomic_fence in V8.
1667 def : Pat<(atomic_fence imm, imm), (STBAR)>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.td | 1304 def AtomicFence : Pseudo<(outs), (ins), "atomic_fence",
1305 [(atomic_fence imm, imm)]>;
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrInfo.td | 883 def : Pat<(atomic_fence (imm), (imm)), (MEMBARRIER)>;
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 413 def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence,
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 493 def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 90 [(atomic_fence (i32 imm:$ordering), (i32 imm:$scope))],
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 2867 def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2868 def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2869 def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
2870 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 475 def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 3149 def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
3150 def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
3151 def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
3152 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 1479 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaInstrInfo.td | 610 def : Pat<(atomic_fence (imm), (imm)), (MB)>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 6163 [(atomic_fence imm:$ordering, 0)]> {
|