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Searched refs:getRegState (Results 1 – 11 of 11) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp597 unsigned RSA = getRegState(AdrOp); in splitMemRef()
702 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg()); in splitCombine()
711 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
728 unsigned RS = getRegState(Op1); in splitExt()
762 unsigned RS = getRegState(Op1); in splitShift()
882 unsigned RS1 = getRegState(Op1); in splitAslOr()
883 unsigned RS2 = getRegState(Op2); in splitAslOr()
DHexagonExpandCondsets.cpp885 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg()); in predicateAt()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp643 unsigned RSA = getRegState(AdrOp); in splitMemRef()
746 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg()); in splitCombine()
754 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
769 unsigned RS = getRegState(Op1); in splitExt()
803 unsigned RS = getRegState(Op1); in splitShift()
923 unsigned RS1 = getRegState(Op1); in splitAslOr()
924 unsigned RS2 = getRegState(Op2); in splitAslOr()
DHexagonExpandCondsets.cpp639 unsigned PredState = getRegState(PredOp) & ~RegState::Kill; in genCondTfrFor()
643 unsigned SrcState = getRegState(SrcOp); in genCondTfrFor()
696 unsigned S = getRegState(ST); in split()
885 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg()); in predicateAt()
DHexagonConstPropagation.cpp2981 .addReg(R1.Reg, getRegState(Acc), R1.SubReg); in rewriteHexConstUses()
3011 .addReg(Src1.getReg(), getRegState(Src1), Src1.getSubReg()) in rewriteHexConstUses()
3012 .addReg(OpR2.getReg(), getRegState(OpR2), OpR2.getSubReg()) in rewriteHexConstUses()
3047 .addReg(SR.Reg, getRegState(SO), SR.SubReg); in rewriteHexConstUses()
3079 .addReg(SR.Reg, getRegState(SO), SR.SubReg); in rewriteHexConstUses()
DHexagonInstrInfo.cpp1253 unsigned PState = getRegState(Op1); in expandPostRAPseudo()
1287 unsigned PState = getRegState(Op1); in expandPostRAPseudo()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DUnreachableBlockElim.cpp221 .addReg(InputReg, getRegState(Input), InputSub); in runOnMachineFunction()
DMachinePipeliner.cpp840 .addReg(RegOp.getReg(), getRegState(RegOp), in preprocessPhiNodes()
/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h395 inline unsigned getRegState(const MachineOperand &RegOp) { in getRegState() function
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h479 inline unsigned getRegState(const MachineOperand &RegOp) { in getRegState() function
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrInfo.cpp4235 unsigned MaskState = getRegState(MIB->getOperand(1)); in expandPostRAPseudo()