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Searched refs:getSUnit (Results 1 – 25 of 56) sorted by relevance

123

/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DScheduleDAG.cpp111 if (!Required && PredDep.getSUnit() == D.getSUnit()) in addPred()
117 SUnit *PredSU = PredDep.getSUnit(); in addPred()
135 SUnit *N = D.getSUnit(); in addPred()
182 SUnit *N = D.getSUnit(); in removePred()
224 SUnit *SuccSU = SuccDep.getSUnit(); in setDepthDirty()
239 SUnit *PredSU = PredDep.getSUnit(); in setHeightDirty()
272 SUnit *PredSU = PredDep.getSUnit(); in ComputeDepth()
303 SUnit *SuccSU = SuccDep.getSUnit(); in ComputeHeight()
329 unsigned MaxDepth = BestI->getSUnit()->getDepth(); in biasCriticalPath()
332 if (I->getKind() == SDep::Data && I->getSUnit()->getDepth() > MaxDepth) in biasCriticalPath()
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DMachinePipeliner.cpp349 return Source->getInstr()->isPHI() || Dep.getSUnit()->getInstr()->isPHI(); in isBackedge()
477 if (Nodes.count(Succ.getSUnit())) in NodeSet()
1023 SUnit *SuccSU = SI.getSUnit(); in isSuccOrder()
1189 SUnit *SU = getSUnit(UseMI); in updatePhiDependences()
1209 SUnit *SU = getSUnit(DefMI); in updatePhiDependences()
1230 MachineInstr *PMI = PI.getSUnit()->getInstr(); in updatePhiDependences()
1264 SUnit *DefSU = getSUnit(DefMI); in changeDependences()
1271 SUnit *LastSU = getSUnit(LastMI); in changeDependences()
1282 if (P->getSUnit() == DefSU) in changeDependences()
1285 Topo.RemovePred(&I, Deps[i].getSUnit()); in changeDependences()
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DMacroFusion.cpp62 if (SI.getSUnit() == &SecondSU) in fuseInstructionPair()
66 if (SI.getSUnit() == &FirstSU) in fuseInstructionPair()
79 SUnit *SU = SI.getSUnit(); in fuseInstructionPair()
92 SUnit *SU = SI.getSUnit(); in fuseInstructionPair()
163 SUnit &DepSU = *Dep.getSUnit(); in scheduleAdjacentImpl()
DLatencyPriorityQueue.cpp61 SUnit &Pred = *I->getSUnit(); in getSingleUnscheduledPred()
80 if (getSingleUnscheduledPred(I->getSUnit()) == SU) in push()
96 AdjustPriorityOfUnscheduledPreds(I->getSUnit()); in scheduledNode()
/external/llvm/lib/CodeGen/
DScheduleDAG.cpp71 if (!Required && I->getSUnit() == D.getSUnit()) in addPred()
76 SUnit *PredSU = I->getSUnit(); in addPred()
95 SUnit *N = D.getSUnit(); in addPred()
141 SUnit *N = D.getSUnit(); in removePred()
187 SUnit *SuccSU = I->getSUnit(); in setDepthDirty()
203 SUnit *PredSU = I->getSUnit(); in setHeightDirty()
244 SUnit *PredSU = I->getSUnit(); in ComputeDepth()
277 SUnit *SuccSU = I->getSUnit(); in ComputeHeight()
303 unsigned MaxDepth = BestI->getSUnit()->getDepth(); in biasCriticalPath()
306 if (I->getKind() == SDep::Data && I->getSUnit()->getDepth() > MaxDepth) in biasCriticalPath()
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DMachinePipeliner.cpp295 return Source->getInstr()->isPHI() || Dep.getSUnit()->getInstr()->isPHI(); in isBackedge()
303 !Dep.getSUnit()->getInstr()->isPHI()); in isOrder()
314 return Dep.getSUnit()->Latency; in getLatency()
315 if (Dep.getSUnit()->getInstr()->isPHI()) in getLatency()
956 SUnit *SuccSU = SI.getSUnit(); in isSuccOrder()
1100 SUnit *SU = getSUnit(UseMI); in updatePhiDependences()
1119 SUnit *SU = getSUnit(DefMI); in updatePhiDependences()
1140 MachineInstr *PMI = PI.getSUnit()->getInstr(); in updatePhiDependences()
1174 SUnit *DefSU = getSUnit(DefMI); in changeDependences()
1181 SUnit *LastSU = getSUnit(LastMI); in changeDependences()
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DLatencyPriorityQueue.cpp60 SUnit &Pred = *I->getSUnit(); in getSingleUnscheduledPred()
79 if (getSingleUnscheduledPred(I->getSUnit()) == SU) in push()
95 AdjustPriorityOfUnscheduledPreds(I->getSUnit()); in scheduledNode()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DGCNMinRegStrategy.cpp97 for (auto PDep : SDep.getSUnit()->Preds) { in getReadySuccessors()
98 auto PSU = PDep.getSUnit(); in getReadySuccessors()
187 if (S.getSUnit()->isBoundaryNode() || isScheduled(S.getSUnit()) || in bumpPredsPriority()
190 for (const auto &P : S.getSUnit()->Preds) { in bumpPredsPriority()
191 auto PSU = P.getSUnit(); in bumpPredsPriority()
203 if (!P.getSUnit()->isBoundaryNode() && !isScheduled(P.getSUnit()) && in bumpPredsPriority()
204 Set.insert(P.getSUnit()).second) in bumpPredsPriority()
205 Worklist.push_back(P.getSUnit()); in bumpPredsPriority()
223 auto SuccSU = S.getSUnit(); in releaseSuccessors()
DSIMachineScheduler.cpp445 if (BC->isSUInBlock(Succ.getSUnit(), ID)) in undoSchedule()
455 SUnit *SuccSU = SuccEdge->getSUnit(); in undoReleaseSucc()
465 SUnit *SuccSU = SuccEdge->getSUnit(); in releaseSucc()
486 SUnit *SuccSU = Succ.getSUnit(); in releaseSuccessors()
519 NodeNum2Index.find(Succ.getSUnit()->NodeNum); in nodeScheduled()
675 if (PredDep.getSUnit() == &FromSU && in hasDataDependencyPred()
831 SUnit *Pred = PredDep.getSUnit(); in colorComputeReservedDependencies()
873 SUnit *Succ = SuccDep.getSUnit(); in colorComputeReservedDependencies()
957 SUnit *Succ = SuccDep.getSUnit(); in colorEndsAccordingToDependencies()
1027 SUnit *Succ = SuccDep.getSUnit(); in colorMergeConstantLoadsNextGroup()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/
DScheduleDAG.cpp97 SUnit *N = D.getSUnit(); in addPred()
134 SUnit *N = D.getSUnit(); in removePred()
177 SUnit *SuccSU = I->getSUnit(); in setDepthDirty()
193 SUnit *PredSU = I->getSUnit(); in setHeightDirty()
234 SUnit *PredSU = I->getSUnit(); in ComputeDepth()
267 SUnit *SuccSU = I->getSUnit(); in ComputeHeight()
317 dbgs() << I->getSUnit() << " - SU(" << I->getSUnit()->NodeNum << ")"; in dumpAll()
338 dbgs() << I->getSUnit() << " - SU(" << I->getSUnit()->NodeNum << ")"; in dumpAll()
465 SUnit *SU = I->getSUnit(); in InitDAGTopologicalSorting()
481 assert(Node2Index[SU->NodeNum] > Node2Index[I->getSUnit()->NodeNum] && in InitDAGTopologicalSorting()
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DLatencyPriorityQueue.cpp59 SUnit &Pred = *I->getSUnit(); in getSingleUnscheduledPred()
78 if (getSingleUnscheduledPred(I->getSUnit()) == SU) in push()
94 AdjustPriorityOfUnscheduledPreds(I->getSUnit()); in ScheduledNode()
DScheduleDAGEmit.cpp40 if (I->getSUnit()->CopyDstRC) { in EmitPhysRegCopy()
42 DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->getSUnit()); in EmitPhysRegCopy()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonSubtarget.cpp156 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply()
163 for (SDep &PI : SI.getSUnit()->Preds) { in apply()
164 if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order) in apply()
167 SI.getSUnit()->setDepthDirty(); in apply()
349 MachineInstr *DDst = Dst->Succs[0].getSUnit()->getInstr(); in adjustSchedDependency()
422 if (!I.isAssignedRegDep() || I.getSUnit() != Dst) in restoreLatency()
461 if (!I.isAssignedRegDep() || I.getSUnit() != Dst) in changeLatency()
478 !I.getSUnit()->getInstr()->isPseudo()) in getZeroLatency()
479 return I.getSUnit(); in getZeroLatency()
556 if (ExclSrc.count(I.getSUnit()) == 0 && in isBestZeroLatency()
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DHexagonHazardRecognizer.cpp146 S.getSUnit()->NumPredsLeft == 1) { in EmitInstruction()
147 UsesDotCur = S.getSUnit(); in EmitInstruction()
161 TII->mayBeNewStore(*S.getSUnit()->getInstr()) && in EmitInstruction()
162 Resources->canReserveResources(*S.getSUnit()->getInstr())) { in EmitInstruction()
163 PrefVectorStoreNew = S.getSUnit(); in EmitInstruction()
DHexagonMachineScheduler.cpp87 if (S.getSUnit() == SUu && S.getLatency() > 0) in hasDependence()
293 unsigned PredReadyCycle = PI.getSUnit()->TopReadyCycle; in releaseTopNode()
312 unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle; in releaseBottomNode()
527 if (!Pred.getSUnit()->isScheduled && (Pred.getSUnit() != SU2)) in isSingleUnscheduledPred()
542 if (!Succ.getSUnit()->isScheduled && (Succ.getSUnit() != SU2)) in isSingleUnscheduledSucc()
647 if (isSingleUnscheduledPred(SI.getSUnit(), SU)) in SchedulingCost()
653 if (isSingleUnscheduledSucc(PI.getSUnit(), SU)) in SchedulingCost()
707 if (!PI.getSUnit()->getInstr()->isPseudo() && PI.isAssignedRegDep() && in SchedulingCost()
709 Top.ResourceModel->isInPacket(PI.getSUnit())) { in SchedulingCost()
716 if (!SI.getSUnit()->getInstr()->isPseudo() && SI.isAssignedRegDep() && in SchedulingCost()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGRRList.cpp227 Topo.AddPred(SU, D.getSUnit()); in AddPred()
235 Topo.RemovePred(SU, D.getSUnit()); in RemovePred()
394 SUnit *PredSU = PredEdge->getSUnit(); in ReleasePred()
559 assert((!RegDef || RegDef == SU || RegDef == Pred.getSUnit()) && in ReleasePredecessors()
561 LiveRegDefs[Pred.getReg()] = Pred.getSUnit(); in ReleasePredecessors()
815 SUnit *PredSU = PredEdge->getSUnit(); in CapturePred()
837 assert(LiveRegDefs[Pred.getReg()] == Pred.getSUnit() && in UnscheduleNodeBottomUp()
893 LiveRegGens[Reg] = Succ.getSUnit(); in UnscheduleNodeBottomUp()
896 Succ2.getSUnit()->getHeight() < LiveRegGens[Reg]->getHeight()) in UnscheduleNodeBottomUp()
897 LiveRegGens[Reg] = Succ2.getSUnit(); in UnscheduleNodeBottomUp()
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DResourcePriorityQueue.cpp74 SUnit *PredSU = Pred.getSUnit(); in numberRCValPredInSU()
111 SUnit *SuccSU = Succ.getSUnit(); in numberRCValSuccInSU()
212 SUnit &PredSU = *Pred.getSUnit(); in getSingleUnscheduledPred()
229 if (getSingleUnscheduledPred(Succ.getSUnit()) == SU) in push()
273 if (Succ.getSUnit() == SU) in isResourceAvailable()
497 if (Pred.isCtrl() || (Pred.getSUnit()->NumRegDefsLeft == 0)) in scheduledNode()
499 --Pred.getSUnit()->NumRegDefsLeft; in scheduledNode()
512 adjustPriorityOfUnscheduledPreds(Succ.getSUnit()); in scheduledNode()
DScheduleDAGFast.cpp142 SUnit *PredSU = PredEdge->getSUnit(); in ReleasePred()
173 LiveRegDefs[Pred.getReg()] = Pred.getSUnit(); in ReleasePredecessors()
196 if (LiveRegCycles[Succ.getReg()] == Succ.getSUnit()->getHeight()) { in ScheduleNodeBottomUp()
287 else if (Pred.getSUnit()->getNode() && in CopyAndMoveSuccessors()
288 Pred.getSUnit()->getNode()->isOperandOf(LoadNode)) in CopyAndMoveSuccessors()
300 if (ChainPred.getSUnit()) { in CopyAndMoveSuccessors()
319 SUnit *SuccDep = D.getSUnit(); in CopyAndMoveSuccessors()
327 SUnit *SuccDep = D.getSUnit(); in CopyAndMoveSuccessors()
364 SUnit *SuccSU = Succ.getSUnit(); in CopyAndMoveSuccessors()
400 SUnit *SuccSU = Succ.getSUnit(); in InsertCopiesAndMoveSuccs()
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/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGRRList.cpp200 Topo.AddPred(SU, D.getSUnit()); in AddPred()
208 Topo.RemovePred(SU, D.getSUnit()); in RemovePred()
366 SUnit *PredSU = PredEdge->getSUnit(); in ReleasePred()
536 assert((!RegDef || RegDef == SU || RegDef == I->getSUnit()) && in ReleasePredecessors()
538 LiveRegDefs[I->getReg()] = I->getSUnit(); in ReleasePredecessors()
792 SUnit *PredSU = PredEdge->getSUnit(); in CapturePred()
814 assert(LiveRegDefs[I->getReg()] == I->getSUnit() && in UnscheduleNodeBottomUp()
864 LiveRegGens[Reg] = Succ.getSUnit(); in UnscheduleNodeBottomUp()
867 Succ2.getSUnit()->getHeight() < LiveRegGens[Reg]->getHeight()) in UnscheduleNodeBottomUp()
868 LiveRegGens[Reg] = Succ2.getSUnit(); in UnscheduleNodeBottomUp()
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DScheduleDAGFast.cpp141 SUnit *PredSU = PredEdge->getSUnit(); in ReleasePred()
173 LiveRegDefs[I->getReg()] = I->getSUnit(); in ReleasePredecessors()
197 if (LiveRegCycles[I->getReg()] == I->getSUnit()->getHeight()) { in ScheduleNodeBottomUp()
289 else if (I->getSUnit()->getNode() && in CopyAndMoveSuccessors()
290 I->getSUnit()->getNode()->isOperandOf(LoadNode)) in CopyAndMoveSuccessors()
303 if (ChainPred.getSUnit()) { in CopyAndMoveSuccessors()
322 SUnit *SuccDep = D.getSUnit(); in CopyAndMoveSuccessors()
330 SUnit *SuccDep = D.getSUnit(); in CopyAndMoveSuccessors()
369 SUnit *SuccSU = I->getSUnit(); in CopyAndMoveSuccessors()
406 SUnit *SuccSU = I->getSUnit(); in InsertCopiesAndMoveSuccs()
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DResourcePriorityQueue.cpp77 SUnit *PredSU = I->getSUnit(); in numberRCValPredInSU()
115 SUnit *SuccSU = I->getSUnit(); in numberRCValSuccInSU()
219 SUnit &Pred = *I->getSUnit(); in getSingleUnscheduledPred()
237 if (getSingleUnscheduledPred(I->getSUnit()) == SU) in push()
281 if (I->getSUnit() == SU) in isResourceAvailable()
511 if (I->isCtrl() || (I->getSUnit()->NumRegDefsLeft == 0)) in scheduledNode()
513 --I->getSUnit()->NumRegDefsLeft; in scheduledNode()
527 adjustPriorityOfUnscheduledPreds(I->getSUnit()); in scheduledNode()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DScheduleDAGRRList.cpp204 Topo.AddPred(SU, D.getSUnit()); in AddPred()
212 Topo.RemovePred(SU, D.getSUnit()); in RemovePred()
367 SUnit *PredSU = PredEdge->getSUnit(); in ReleasePred()
434 assert((!RegDef || RegDef == SU || RegDef == I->getSUnit()) && in ReleasePredecessors()
436 LiveRegDefs[I->getReg()] = I->getSUnit(); in ReleasePredecessors()
659 SUnit *PredSU = PredEdge->getSUnit(); in CapturePred()
681 assert(LiveRegDefs[I->getReg()] == I->getSUnit() && in UnscheduleNodeBottomUp()
699 I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight()) in UnscheduleNodeBottomUp()
700 LiveRegGens[I->getReg()] = I->getSUnit(); in UnscheduleNodeBottomUp()
863 else if (isOperandOf(I->getSUnit(), LoadNode)) in CopyAndMoveSuccessors()
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DScheduleDAGFast.cpp135 SUnit *PredSU = PredEdge->getSUnit(); in ReleasePred()
167 LiveRegDefs[I->getReg()] = I->getSUnit(); in ReleasePredecessors()
191 if (LiveRegCycles[I->getReg()] == I->getSUnit()->getHeight()) { in ScheduleNodeBottomUp()
284 else if (I->getSUnit()->getNode() && in CopyAndMoveSuccessors()
285 I->getSUnit()->getNode()->isOperandOf(LoadNode)) in CopyAndMoveSuccessors()
298 if (ChainPred.getSUnit()) { in CopyAndMoveSuccessors()
317 SUnit *SuccDep = D.getSUnit(); in CopyAndMoveSuccessors()
325 SUnit *SuccDep = D.getSUnit(); in CopyAndMoveSuccessors()
362 SUnit *SuccSU = I->getSUnit(); in CopyAndMoveSuccessors()
399 SUnit *SuccSU = I->getSUnit(); in InsertCopiesAndMoveSuccs()
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/external/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp75 if (I->getSUnit() == SU) in isResourceAvailable()
234 unsigned PredReadyCycle = I->getSUnit()->TopReadyCycle; in releaseTopNode()
253 unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle; in releaseBottomNode()
435 SUnit &Pred = *I->getSUnit(); in getSingleUnscheduledPred()
453 SUnit &Succ = *I->getSUnit(); in getSingleUnscheduledSucc()
514 if (getSingleUnscheduledPred(I->getSUnit()) == SU) in SchedulingCost()
520 if (getSingleUnscheduledSucc(I->getSUnit()) == SU) in SchedulingCost()
/external/llvm/lib/Target/AMDGPU/
DSIMachineScheduler.cpp424 if (BC->isSUInBlock(Succ.getSUnit(), ID)) in undoSchedule()
434 SUnit *SuccSU = SuccEdge->getSUnit(); in undoReleaseSucc()
444 SUnit *SuccSU = SuccEdge->getSUnit(); in releaseSucc()
465 SUnit *SuccSU = Succ.getSUnit(); in releaseSuccessors()
496 NodeNum2Index.find(Succ.getSUnit()->NodeNum); in nodeScheduled()
722 SUnit *Pred = PredDep.getSUnit(); in colorComputeReservedDependencies()
764 SUnit *Succ = SuccDep.getSUnit(); in colorComputeReservedDependencies()
837 SUnit *Succ = SuccDep.getSUnit(); in colorEndsAccordingToDependencies()
904 SUnit *Succ = SuccDep.getSUnit(); in colorMergeConstantLoadsNextGroup()
925 SUnit *Succ = SuccDep.getSUnit(); in colorMergeIfPossibleNextGroup()
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