| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | CallingConvLower.cpp | 73 if (ValAssign.isRegLoc()) { in IsShadowAllocatedReg()
232 HaveRegParm = Locs.back().isRegLoc(); in getRemainingRegParmsForType()
238 if (Locs[I].isRegLoc()) in getRemainingRegParmsForType()
292 bool RegLoc1 = Loc1.isRegLoc(); in resultsCompatible()
293 if (RegLoc1 != Loc2.isRegLoc()) in resultsCompatible()
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| /external/llvm/lib/CodeGen/ |
| D | CallingConvLower.cpp | 215 HaveRegParm = Locs.back().isRegLoc(); in getRemainingRegParmsForType()
221 if (Locs[I].isRegLoc()) in getRemainingRegParmsForType()
275 bool RegLoc1 = Loc1.isRegLoc(); in resultsCompatible()
276 if (RegLoc1 != Loc2.isRegLoc()) in resultsCompatible()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 116 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg"); in assignValueToReg()
152 assert(VA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
153 assert(NextVA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
343 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg"); in assignValueToReg()
381 assert(VA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
382 assert(NextVA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
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| D | ARMFastISel.cpp | 1920 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1926 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) in ProcessCallArgs()
2001 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
2013 assert(VA.isRegLoc() && NextVA.isRegLoc() && in ProcessCallArgs()
2142 if (!VA.isRegLoc()) in SelectRet()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/ |
| D | Nios2ISelLowering.cpp | 52 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
109 if (VA.isRegLoc()) { in LowerFormalArguments()
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 116 bool isRegLoc() const { return !isMem; } in isRegLoc() function
121 unsigned getLocReg() const { assert(isRegLoc()); return Loc; } in getLocReg()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
| D | ARCISelLowering.cpp | 286 if (VA.isRegLoc()) { in LowerCall()
379 if (VA.isRegLoc()) { in lowerCallResult()
484 if (VA.isRegLoc()) { in LowerCallArguments()
634 if (VA.isRegLoc()) in LowerReturn()
662 if (!VA.isRegLoc()) in LowerReturn()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 82 assert(VA.isRegLoc() && "Not yet implemented"); in lowerFormalArguments()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 143 bool isRegLoc() const { return !isMem; } in isRegLoc() function
148 unsigned getLocReg() const { assert(isRegLoc()); return Loc; } in getLocReg()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 144 bool isRegLoc() const { return !isMem; } in isRegLoc() function
149 unsigned getLocReg() const { assert(isRegLoc()); return Loc; } in getLocReg()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.cpp | 184 if (VA.isRegLoc()) { in LowerFormalArguments()
252 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
329 if (VA.isRegLoc()) { in LowerCall()
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 308 if (VA.isRegLoc()) { in LowerCCCArguments()
428 if (VA.isRegLoc()) { in LowerCCCCallTo()
574 if (RVLocs[i].isRegLoc()) in LowerReturn()
584 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 172 if (VA.isRegLoc()) { in LowerFormalArguments()
290 if (VA.isRegLoc()) in LowerCall()
373 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 103 if (RVLocs[i].isRegLoc()) in LowerReturn()
112 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
183 if (VA.isRegLoc()) { in LowerFormalArguments()
478 if (VA.isRegLoc()) { in LowerCall()
482 if (NextVA.isRegLoc()) { in LowerCall()
515 if (VA.isRegLoc()) { in LowerCall()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 934 assert(VA.isRegLoc() && "Expected register VA assignment"); in unpackF64OnRV32DSoftABI()
1004 else if (VA.isRegLoc()) in LowerFormalArguments()
1255 if (IsF64OnRV32DSoftABI && VA.isRegLoc()) { in LowerCall()
1323 if (VA.isRegLoc()) { in LowerCall()
1498 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
1502 assert(VA.isRegLoc() && "Expected return via registers"); in LowerReturn()
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 741 if (VA.isRegLoc()) { in LowerCall()
895 if (VA.isRegLoc()) { in LowerFormalArguments()
1027 if (RVLocs[i].isRegLoc()) in LowerReturn()
1036 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 226 if (VA.isRegLoc()) { in LowerFormalArguments()
348 if (VA.isRegLoc()) in LowerCall()
435 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CallLowering.cpp | 138 if (VA.isRegLoc()) in handleAssignments()
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 324 if (VA.isRegLoc()) { in LowerCCCArguments()
409 if (RVLocs[i].isRegLoc()) in LowerReturn()
418 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
491 if (VA.isRegLoc()) { in LowerCCCCallTo()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1894 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1900 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) in ProcessCallArgs()
1975 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1986 assert(VA.isRegLoc() && NextVA.isRegLoc() && in ProcessCallArgs()
2115 if (!VA.isRegLoc()) in SelectRet()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 233 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
316 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_64()
415 if (VA.isRegLoc()) { in LowerFormalArguments_32()
602 if (VA.isRegLoc()) { in LowerFormalArguments_64()
874 if (VA.isRegLoc()) { in LowerCall_32()
878 if (NextVA.isRegLoc()) { in LowerCall_32()
911 if (VA.isRegLoc()) { in LowerCall_32()
1109 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) in fixupVariableFloatArgs()
1222 if (VA.isRegLoc()) { in LowerCall_64()
1260 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() && in LowerCall_64()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 235 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
318 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_64()
416 if (VA.isRegLoc()) { in LowerFormalArguments_32()
595 if (VA.isRegLoc()) { in LowerFormalArguments_64()
864 if (VA.isRegLoc()) { in LowerCall_32()
868 if (NextVA.isRegLoc()) { in LowerCall_32()
898 if (VA.isRegLoc()) { in LowerCall_32()
1095 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) in fixupVariableFloatArgs()
1207 if (VA.isRegLoc()) { in LowerCall_64()
1242 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() && in LowerCall_64()
|
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 946 if (VA.isRegLoc()) { in LowerCCCCallTo()
1102 if (VA.isRegLoc()) { in LowerCCCArguments()
1225 if (RVLocs[i].isRegLoc()) in LowerReturn()
1234 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1078 if (VA.isRegLoc()) { in LowerCallResult()
1173 if (VA.isRegLoc()) { in LowerCCCCallTo()
1310 if (VA.isRegLoc()) { in LowerCCCArguments()
1482 if (VA.isRegLoc()) in LowerReturn()
1511 if (!VA.isRegLoc()) in LowerReturn()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1063 if (VA.isRegLoc()) { in LowerCallResult()
1157 if (VA.isRegLoc()) { in LowerCCCCallTo()
1294 if (VA.isRegLoc()) { in LowerCCCArguments()
1465 if (VA.isRegLoc()) in LowerReturn()
1493 if (!VA.isRegLoc()) in LowerReturn()
|