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Searched refs:no_shift (Results 1 – 25 of 29) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelDAGToDAG.cpp401 if (ShOpcVal == ARM_AM::no_shift) return false; in SelectImmShifterOperand()
425 if (ShOpcVal == ARM_AM::no_shift) return false; in SelectRegShifterOperand()
539 if (ShOpcVal != ARM_AM::no_shift) { in SelectLdStSOReg()
549 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
552 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
557 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift && in SelectLdStSOReg()
560 if (ShOpcVal != ARM_AM::no_shift) { in SelectLdStSOReg()
571 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
574 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
631 ARM_AM::no_shift), in SelectAddrMode2Worker()
[all …]
DARMSelectionDAGInfo.h25 default: return ARM_AM::no_shift; in getShiftOpcForNode()
DARMLoadStoreOptimizer.cpp917 int Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); in MergeBaseUpdateLoadStore()
935 int Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); in MergeBaseUpdateLoadStore()
DARMFrameLowering.cpp680 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift)); in emitPopInst()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp2629 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 }, in ARMEmitIntExt()
2630 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } }, in ARMEmitIntExt()
2631 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 }, in ARMEmitIntExt()
2632 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } }, in ARMEmitIntExt()
2633 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 }, in ARMEmitIntExt()
2634 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } } in ARMEmitIntExt()
2639 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2640 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } }, in ARMEmitIntExt()
2641 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2642 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } }, in ARMEmitIntExt()
[all …]
DARMSelectionDAGInfo.h26 default: return ARM_AM::no_shift; in getShiftOpcForNode()
DARMISelDAGToDAG.cpp558 if (ShOpcVal == ARM_AM::no_shift) return false; in SelectImmShifterOperand()
582 if (ShOpcVal == ARM_AM::no_shift) return false; in SelectRegShifterOperand()
699 if (ShOpcVal != ARM_AM::no_shift) { in SelectLdStSOReg()
709 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
712 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
717 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift && in SelectLdStSOReg()
721 if (ShOpcVal != ARM_AM::no_shift) { in SelectLdStSOReg()
732 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
735 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
804 ARM_AM::no_shift), in SelectAddrMode2Worker()
[all …]
DARMLoadStoreOptimizer.cpp1400 int Imm = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); in MergeBaseUpdateLoadStore()
1417 int Imm = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); in MergeBaseUpdateLoadStore()
DARMFrameLowering.cpp1039 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift)); in emitPopInst()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMFastISel.cpp2655 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 }, in ARMEmitIntExt()
2656 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } }, in ARMEmitIntExt()
2657 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 }, in ARMEmitIntExt()
2658 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } }, in ARMEmitIntExt()
2659 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 }, in ARMEmitIntExt()
2660 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } } in ARMEmitIntExt()
2665 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2666 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } }, in ARMEmitIntExt()
2667 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2668 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } }, in ARMEmitIntExt()
[all …]
DARMSelectionDAGInfo.h26 default: return ARM_AM::no_shift; in getShiftOpcForNode()
DARMISelDAGToDAG.cpp536 if (ShOpcVal == ARM_AM::no_shift) return false; in SelectImmShifterOperand()
560 if (ShOpcVal == ARM_AM::no_shift) return false; in SelectRegShifterOperand()
685 if (ShOpcVal != ARM_AM::no_shift) { in SelectLdStSOReg()
695 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
698 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
703 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift && in SelectLdStSOReg()
707 if (ShOpcVal != ARM_AM::no_shift) { in SelectLdStSOReg()
718 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
721 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
760 if (ShOpcVal != ARM_AM::no_shift) { in SelectAddrMode2OffsetReg()
[all …]
DARMLoadStoreOptimizer.cpp1434 int Imm = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); in MergeBaseUpdateLoadStore()
1456 int Imm = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); in MergeBaseUpdateLoadStore()
DARMBaseInstrInfo.cpp592 return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift; in isLdstScaledReg()
604 if (ShiftOpc == ARM_AM::no_shift) return false; // not scaled in isLdstScaledRegNotPlusLsl2()
620 return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift; in isAm2ScaledReg()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp675 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift; in isPostIdxReg()
708 if (Memory.ShiftType != ARM_AM::no_shift) return false; in isAddrMode3()
720 return PostIdxReg.ShiftTy == ARM_AM::no_shift; in isAM3Offset()
740 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemTBB()
761 if (Memory.ShiftType == ARM_AM::no_shift) in isT2MemRegOffset()
771 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemThumbRR()
1171 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAddrMode2Operands()
1192 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAM2OffsetImmOperands()
1715 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) in print()
1875 .Default(ARM_AM::no_shift); in tryParseShiftRegister()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h27 no_shift = 0, enumerator
DARMMCCodeEmitter.cpp181 case ARM_AM::no_shift: in getShiftOp()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h28 no_shift = 0, enumerator
DARMMCCodeEmitter.cpp221 case ARM_AM::no_shift: in getShiftOp()
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h28 no_shift = 0, enumerator
DARMMCCodeEmitter.cpp207 case ARM_AM::no_shift: in getShiftOp()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp1088 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; in isPostIdxReg()
1195 if (Memory.ShiftType != ARM_AM::no_shift) return false; in isAddrMode3()
1209 return PostIdxReg.ShiftTy == ARM_AM::no_shift; in isAM3Offset()
1248 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemTBB()
1269 if (Memory.ShiftType == ARM_AM::no_shift) in isT2MemRegOffset()
1279 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemThumbRR()
2126 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAddrMode2Operands()
2147 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAM2OffsetImmOperands()
2929 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) in print()
3105 .Default(ARM_AM::no_shift); in tryParseShiftRegister()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp1240 return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift; in isPostIdxReg()
1364 if (Memory.ShiftType != ARM_AM::no_shift) return false; in isAddrMode3()
1424 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemTBB()
1448 if (Memory.ShiftType == ARM_AM::no_shift) in isT2MemRegOffset()
1459 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemThumbRR()
2398 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAddrMode2Operands()
2419 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAM2OffsetImmOperands()
3257 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) in print()
3432 .Default(ARM_AM::no_shift); in tryParseShiftRegister()
3434 if (ShiftTy == ARM_AM::no_shift) in tryParseShiftRegister()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp55 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) in printRegImmShift()
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp46 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) in printRegImmShift()

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