| /external/llvm/test/CodeGen/ARM/ |
| D | copy-cpsr.ll | 6 ; escape. However, for long ADCS chains (and last ditch fallback) the dependency
12 ; + We want 2 long ADCS chains
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | copy-cpsr.ll | 6 ; escape. However, for long ADCS chains (and last ditch fallback) the dependency
12 ; + We want 2 long ADCS chains
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | nzcv-save.ll | 6 ; DAG ends up with two uses for the flags from an ADCS node, which means they
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| /external/llvm/test/CodeGen/AArch64/ |
| D | nzcv-save.ll | 6 ; DAG ends up with two uses for the flags from an ADCS node, which means they
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 487 ADCS r5, r2, r1 // Must be wide - 3 distinct registers
488 ADCS r5, r5, r1 // Should choose narrow
489 ADCS r3, r1, r3 // Should choose narrow - commutative
490 ADCS.W r2, r2, r1 // Explicitly wide
491 ADCS.W r3, r1, r3
493 ADCS r7, r7, r1 // Should use narrow
494 ADCS r7, r1, r7 // Commutative
495 ADCS r8, r1, r8 // high registers so must use wide encoding
496 ADCS r8, r8, r1
497 ADCS r5, r8, r5
[all …]
|
| /external/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 487 ADCS r5, r2, r1 // Must be wide - 3 distinct registers
488 ADCS r5, r5, r1 // Should choose narrow
489 ADCS r3, r1, r3 // Should choose narrow - commutative
490 ADCS.W r2, r2, r1 // Explicitly wide
491 ADCS.W r3, r1, r3
493 ADCS r7, r7, r1 // Should use narrow
494 ADCS r7, r1, r7 // Commutative
495 ADCS r8, r1, r8 // high registers so must use wide encoding
496 ADCS r8, r8, r1
497 ADCS r5, r8, r5
[all …]
|
| /external/vixl/test/aarch32/config/ |
| D | cond-rd-rn-operand-rm-t32.json | 48 "Adcs", // ADCS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
49 // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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| D | cond-rd-rn-operand-const-a32.json | 30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
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| D | cond-rd-rn-operand-const-t32.json | 37 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
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| D | cond-rd-rn-operand-rm-shift-rs-a32.json | 30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
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| D | cond-rd-rn-operand-rm-shift-amount-1to32-a32.json | 30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
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| D | cond-rd-rn-operand-rm-shift-amount-1to31-a32.json | 30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
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| D | cond-rd-rn-operand-rm-shift-amount-1to32-t32.json | 34 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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| D | cond-rd-rn-operand-rm-shift-amount-1to31-t32.json | 34 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
|
| D | cond-rd-rn-operand-rm-a32.json | 39 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 58 ADCS, enumerator
|
| D | AArch64ISelLowering.cpp | 853 case AArch64ISD::ADCS: return "AArch64ISD::ADCS"; in getTargetNodeName()
1816 Opc = AArch64ISD::ADCS; in LowerADDC_ADDE_SUBC_SUBE()
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| D | AArch64InstrInfo.td | 185 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 58 ADCS, enumerator
|
| D | AArch64ISelLowering.cpp | 1104 case AArch64ISD::ADCS: return "AArch64ISD::ADCS"; in getTargetNodeName()
2140 Opc = AArch64ISD::ADCS; in LowerADDC_ADDE_SUBC_SUBE()
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| D | AArch64InstrInfo.td | 216 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_T2_32.c | 95 #define ADCS 0x4140 macro
787 return push_inst16(compiler, ADCS | RD3(dst) | RN3(arg2)); in emit_op_imm()
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 19 ### ADCS ### subsection
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenDAGISel.inc | 33221 /* 63465*/ /*SwitchOpcode*/ 33, TARGET_VAL(AArch64ISD::ADCS),// ->63501
|