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Searched refs:Mips (Results 1 – 25 of 426) sorted by relevance

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/external/llvm-project/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp29 return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM; in getUnconditionalBranch()
30 return STI.isPositionIndependent() ? Mips::B : Mips::J; in getUnconditionalBranch()
49 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
71 if ((Opc == Mips::SW) || (Opc == Mips::SD) || in isStoreToStackSlot()
72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
91 if (Mips::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
93 Opc = Mips::MOVE16_MM; in copyPhysReg()
95 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
[all …]
DMipsInstrInfo.cpp41 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), in MipsInstrInfo()
62 BuildMI(MBB, MI, DL, get(Mips::NOP)); in insertNoop()
282 case Mips::B: in isBranchOffsetInRange()
283 case Mips::BAL: in isBranchOffsetInRange()
284 case Mips::BAL_BR: in isBranchOffsetInRange()
285 case Mips::BAL_BR_MM: in isBranchOffsetInRange()
286 case Mips::BC1F: in isBranchOffsetInRange()
287 case Mips::BC1FL: in isBranchOffsetInRange()
288 case Mips::BC1T: in isBranchOffsetInRange()
289 case Mips::BC1TL: in isBranchOffsetInRange()
[all …]
DMipsExpandPseudo.cpp84 unsigned ZERO = Mips::ZERO; in expandAtomicCmpSwapSubword()
85 unsigned BNE = Mips::BNE; in expandAtomicCmpSwapSubword()
86 unsigned BEQ = Mips::BEQ; in expandAtomicCmpSwapSubword()
88 I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I8_POSTRA ? Mips::SEB : Mips::SEH; in expandAtomicCmpSwapSubword()
91 LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM; in expandAtomicCmpSwapSubword()
92 SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM; in expandAtomicCmpSwapSubword()
93 BNE = STI->hasMips32r6() ? Mips::BNEC_MMR6 : Mips::BNE_MM; in expandAtomicCmpSwapSubword()
94 BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM; in expandAtomicCmpSwapSubword()
96 LL = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) in expandAtomicCmpSwapSubword()
97 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); in expandAtomicCmpSwapSubword()
[all …]
DMips16InstrInfo.cpp43 : MipsInstrInfo(STI, Mips::Bimm16) {} in Mips16InstrInfo()
75 if (Mips::CPU16RegsRegClass.contains(DestReg) && in copyPhysReg()
76 Mips::GPR32RegClass.contains(SrcReg)) in copyPhysReg()
77 Opc = Mips::MoveR3216; in copyPhysReg()
78 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
79 Mips::CPU16RegsRegClass.contains(SrcReg)) in copyPhysReg()
80 Opc = Mips::Move32R16; in copyPhysReg()
81 else if ((SrcReg == Mips::HI0) && in copyPhysReg()
82 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
83 Opc = Mips::Mfhi16, SrcReg = 0; in copyPhysReg()
[all …]
DMipsRegisterInfo.cpp42 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {} in MipsRegisterInfo()
44 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; } in getPICCallReg()
54 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
56 return &Mips::GPRMM16RegClass; in getPointerRegClass()
58 return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass; in getPointerRegClass()
60 return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass; in getPointerRegClass()
72 case Mips::GPR32RegClassID: in getRegPressureLimit()
73 case Mips::GPR64RegClassID: in getRegPressureLimit()
74 case Mips::DSPRRegClassID: { in getRegPressureLimit()
78 case Mips::FGR32RegClassID: in getRegPressureLimit()
[all …]
DMicroMipsSizeReduction.cpp214 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM),
216 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM), ReduceADDIUToADDIUSP,
218 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUR1SP_MM),
220 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUSP_MM),
222 {RT_OneInstr, OpCodes(Mips::ADDu, Mips::ADDU16_MM),
225 {RT_OneInstr, OpCodes(Mips::ADDu_MM, Mips::ADDU16_MM),
228 {RT_OneInstr, OpCodes(Mips::LBu, Mips::LBU16_MM), ReduceLXUtoLXU16,
230 {RT_OneInstr, OpCodes(Mips::LBu_MM, Mips::LBU16_MM), ReduceLXUtoLXU16,
232 {RT_OneInstr, OpCodes(Mips::LEA_ADDiu, Mips::ADDIUR1SP_MM),
234 {RT_OneInstr, OpCodes(Mips::LEA_ADDiu_MM, Mips::ADDIUR1SP_MM),
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp29 return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM; in getUnconditionalBranch()
30 return STI.isPositionIndependent() ? Mips::B : Mips::J; in getUnconditionalBranch()
49 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
71 if ((Opc == Mips::SW) || (Opc == Mips::SD) || in isStoreToStackSlot()
72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
91 if (Mips::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
93 Opc = Mips::MOVE16_MM; in copyPhysReg()
95 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
[all …]
DMipsInstrInfo.cpp40 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), in MipsInstrInfo()
61 BuildMI(MBB, MI, DL, get(Mips::NOP)); in insertNoop()
281 case Mips::B: in isBranchOffsetInRange()
282 case Mips::BAL: in isBranchOffsetInRange()
283 case Mips::BAL_BR: in isBranchOffsetInRange()
284 case Mips::BAL_BR_MM: in isBranchOffsetInRange()
285 case Mips::BC1F: in isBranchOffsetInRange()
286 case Mips::BC1FL: in isBranchOffsetInRange()
287 case Mips::BC1T: in isBranchOffsetInRange()
288 case Mips::BC1TL: in isBranchOffsetInRange()
[all …]
DMipsExpandPseudo.cpp84 unsigned ZERO = Mips::ZERO; in expandAtomicCmpSwapSubword()
85 unsigned BNE = Mips::BNE; in expandAtomicCmpSwapSubword()
86 unsigned BEQ = Mips::BEQ; in expandAtomicCmpSwapSubword()
88 I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I8_POSTRA ? Mips::SEB : Mips::SEH; in expandAtomicCmpSwapSubword()
91 LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM; in expandAtomicCmpSwapSubword()
92 SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM; in expandAtomicCmpSwapSubword()
93 BNE = STI->hasMips32r6() ? Mips::BNEC_MMR6 : Mips::BNE_MM; in expandAtomicCmpSwapSubword()
94 BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM; in expandAtomicCmpSwapSubword()
96 LL = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) in expandAtomicCmpSwapSubword()
97 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); in expandAtomicCmpSwapSubword()
[all …]
DMips16InstrInfo.cpp43 : MipsInstrInfo(STI, Mips::Bimm16) {} in Mips16InstrInfo()
75 if (Mips::CPU16RegsRegClass.contains(DestReg) && in copyPhysReg()
76 Mips::GPR32RegClass.contains(SrcReg)) in copyPhysReg()
77 Opc = Mips::MoveR3216; in copyPhysReg()
78 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
79 Mips::CPU16RegsRegClass.contains(SrcReg)) in copyPhysReg()
80 Opc = Mips::Move32R16; in copyPhysReg()
81 else if ((SrcReg == Mips::HI0) && in copyPhysReg()
82 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
83 Opc = Mips::Mfhi16, SrcReg = 0; in copyPhysReg()
[all …]
DMipsRegisterInfo.cpp42 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {} in MipsRegisterInfo()
44 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; } in getPICCallReg()
54 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
56 return &Mips::GPRMM16RegClass; in getPointerRegClass()
58 return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass; in getPointerRegClass()
60 return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass; in getPointerRegClass()
72 case Mips::GPR32RegClassID: in getRegPressureLimit()
73 case Mips::GPR64RegClassID: in getRegPressureLimit()
74 case Mips::DSPRRegClassID: { in getRegPressureLimit()
78 case Mips::FGR32RegClassID: in getRegPressureLimit()
[all …]
DMicroMipsSizeReduction.cpp214 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM),
216 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM), ReduceADDIUToADDIUSP,
218 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUR1SP_MM),
220 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUSP_MM),
222 {RT_OneInstr, OpCodes(Mips::ADDu, Mips::ADDU16_MM),
225 {RT_OneInstr, OpCodes(Mips::ADDu_MM, Mips::ADDU16_MM),
228 {RT_OneInstr, OpCodes(Mips::LBu, Mips::LBU16_MM), ReduceLXUtoLXU16,
230 {RT_OneInstr, OpCodes(Mips::LBu_MM, Mips::LBU16_MM), ReduceLXUtoLXU16,
232 {RT_OneInstr, OpCodes(Mips::LEA_ADDiu, Mips::ADDIUR1SP_MM),
234 {RT_OneInstr, OpCodes(Mips::LEA_ADDiu_MM, Mips::ADDIUR1SP_MM),
[all …]
/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp29 : MipsInstrInfo(STI, STI.isPositionIndependent() ? Mips::B : Mips::J), in MipsSEInstrInfo()
45 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
67 if ((Opc == Mips::SW) || (Opc == Mips::SD) || in isStoreToStackSlot()
68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
86 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
87 if (Mips::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
89 Opc = Mips::MOVE16_MM; in copyPhysReg()
91 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
92 } else if (Mips::CCRRegClass.contains(SrcReg)) in copyPhysReg()
[all …]
DMips16InstrInfo.cpp33 : MipsInstrInfo(STI, Mips::Bimm16), RI() {} in Mips16InstrInfo()
65 if (Mips::CPU16RegsRegClass.contains(DestReg) && in copyPhysReg()
66 Mips::GPR32RegClass.contains(SrcReg)) in copyPhysReg()
67 Opc = Mips::MoveR3216; in copyPhysReg()
68 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
69 Mips::CPU16RegsRegClass.contains(SrcReg)) in copyPhysReg()
70 Opc = Mips::Move32R16; in copyPhysReg()
71 else if ((SrcReg == Mips::HI0) && in copyPhysReg()
72 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
73 Opc = Mips::Mfhi16, SrcReg = 0; in copyPhysReg()
[all …]
DMipsRegisterInfo.cpp45 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {} in MipsRegisterInfo()
47 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; } in getPICCallReg()
57 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
59 return ABI.ArePtrs64bit() ? &Mips::GPRMM16_64RegClass in getPointerRegClass()
60 : &Mips::GPRMM16RegClass; in getPointerRegClass()
62 return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass; in getPointerRegClass()
64 return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass; in getPointerRegClass()
76 case Mips::GPR32RegClassID: in getRegPressureLimit()
77 case Mips::GPR64RegClassID: in getRegPressureLimit()
78 case Mips::DSPRRegClassID: { in getRegPressureLimit()
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenRegisterInfo.inc18 namespace Mips {
464 } // end namespace Mips
468 namespace Mips {
542 } // end namespace Mips
547 namespace Mips {
563 } // end namespace Mips
1591 { Mips::AT },
1592 { Mips::DSPCCond },
1593 { Mips::DSPCarry },
1594 { Mips::DSPEFI },
[all …]
DMipsGenRegisterBank.inc12 namespace Mips {
18 } // end namespace Mips
35 namespace Mips {
38 (1u << (Mips::FGR32RegClassID - 0)) |
39 (1u << (Mips::FGRCCRegClassID - 0)) |
42 (1u << (Mips::FGR64RegClassID - 32)) |
43 (1u << (Mips::AFGR64RegClassID - 32)) |
46 (1u << (Mips::MSA128DRegClassID - 64)) |
47 (1u << (Mips::MSA128BRegClassID - 64)) |
48 (1u << (Mips::MSA128HRegClassID - 64)) |
[all …]
DMipsGenMCCodeEmitter.inc2771 case Mips::Break16:
2772 case Mips::DERET:
2773 case Mips::DERET_MM:
2774 case Mips::DERET_MMR6:
2775 case Mips::EHB:
2776 case Mips::EHB_MM:
2777 case Mips::EHB_MMR6:
2778 case Mips::ERET:
2779 case Mips::ERETNC:
2780 case Mips::ERETNC_MMR6:
[all …]
/external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
DMipsAsmBackend.cpp48 case Mips::fixup_Mips_LO16: in adjustFixupValue()
49 case Mips::fixup_Mips_GPREL16: in adjustFixupValue()
50 case Mips::fixup_Mips_GPOFF_HI: in adjustFixupValue()
51 case Mips::fixup_Mips_GPOFF_LO: in adjustFixupValue()
52 case Mips::fixup_Mips_GOT_PAGE: in adjustFixupValue()
53 case Mips::fixup_Mips_GOT_OFST: in adjustFixupValue()
54 case Mips::fixup_Mips_GOT_DISP: in adjustFixupValue()
55 case Mips::fixup_Mips_GOT_LO16: in adjustFixupValue()
56 case Mips::fixup_Mips_CALL_LO16: in adjustFixupValue()
57 case Mips::fixup_MICROMIPS_GPOFF_HI: in adjustFixupValue()
[all …]
DMipsABIInfo.cpp26 static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
29 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
30 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
75 return ArePtrs64bit() ? Mips::SP_64 : Mips::SP; in GetStackPtr()
79 return ArePtrs64bit() ? Mips::FP_64 : Mips::FP; in GetFramePtr()
83 return ArePtrs64bit() ? Mips::S7_64 : Mips::S7; in GetBasePtr()
87 return ArePtrs64bit() ? Mips::GP_64 : Mips::GP; in GetGlobalPtr()
91 return ArePtrs64bit() ? Mips::ZERO_64 : Mips::ZERO; in GetNullPtr()
95 return AreGprs64bit() ? Mips::ZERO_64 : Mips::ZERO; in GetZeroReg()
99 return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu; in GetPtrAdduOp()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsAsmBackend.cpp48 case Mips::fixup_Mips_LO16: in adjustFixupValue()
49 case Mips::fixup_Mips_GPREL16: in adjustFixupValue()
50 case Mips::fixup_Mips_GPOFF_HI: in adjustFixupValue()
51 case Mips::fixup_Mips_GPOFF_LO: in adjustFixupValue()
52 case Mips::fixup_Mips_GOT_PAGE: in adjustFixupValue()
53 case Mips::fixup_Mips_GOT_OFST: in adjustFixupValue()
54 case Mips::fixup_Mips_GOT_DISP: in adjustFixupValue()
55 case Mips::fixup_Mips_GOT_LO16: in adjustFixupValue()
56 case Mips::fixup_Mips_CALL_LO16: in adjustFixupValue()
57 case Mips::fixup_MICROMIPS_GPOFF_HI: in adjustFixupValue()
[all …]
DMipsABIInfo.cpp26 static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
29 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
30 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
75 return ArePtrs64bit() ? Mips::SP_64 : Mips::SP; in GetStackPtr()
79 return ArePtrs64bit() ? Mips::FP_64 : Mips::FP; in GetFramePtr()
83 return ArePtrs64bit() ? Mips::S7_64 : Mips::S7; in GetBasePtr()
87 return ArePtrs64bit() ? Mips::GP_64 : Mips::GP; in GetGlobalPtr()
91 return ArePtrs64bit() ? Mips::ZERO_64 : Mips::ZERO; in GetNullPtr()
95 return AreGprs64bit() ? Mips::ZERO_64 : Mips::ZERO; in GetZeroReg()
99 return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu; in GetPtrAdduOp()
[all …]
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsABIInfo.cpp19 static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
22 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
23 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
67 return ArePtrs64bit() ? Mips::SP_64 : Mips::SP; in GetStackPtr()
71 return ArePtrs64bit() ? Mips::FP_64 : Mips::FP; in GetFramePtr()
75 return ArePtrs64bit() ? Mips::S7_64 : Mips::S7; in GetBasePtr()
79 return ArePtrs64bit() ? Mips::GP_64 : Mips::GP; in GetGlobalPtr()
83 return ArePtrs64bit() ? Mips::ZERO_64 : Mips::ZERO; in GetNullPtr()
87 return AreGprs64bit() ? Mips::ZERO_64 : Mips::ZERO; in GetZeroReg()
91 return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu; in GetPtrAdduOp()
[all …]
/external/llvm-project/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp122 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
123 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
124 Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5,
125 Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2,
126 Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
127 Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
128 Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
129 Mips::FeatureCnMipsP, Mips::FeatureFP64Bit, Mips::FeatureGP64Bit,
130 Mips::FeatureNaN2008
577 return getSTI().getFeatureBits()[Mips::FeatureGP64Bit]; in isGP64bit()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp122 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
123 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
124 Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5,
125 Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2,
126 Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
127 Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
128 Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
129 Mips::FeatureCnMipsP, Mips::FeatureFP64Bit, Mips::FeatureGP64Bit,
130 Mips::FeatureNaN2008
561 return getSTI().getFeatureBits()[Mips::FeatureGP64Bit]; in isGP64bit()
[all …]

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