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Searched refs:TMP3 (Results 1 – 25 of 704) sorted by relevance

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/external/boringssl/src/crypto/cipher_extra/asm/
Daes128gcmsiv-x86_64.pl87 my $TMP3 = "%xmm4";
98 vpclmulqdq \$0x01, $TMP0, $T, $TMP3
99 vpxor $TMP3, $TMP2, $TMP2
100 vpslldq \$8, $TMP2, $TMP3
102 vpxor $TMP3, $TMP1, $TMP1
106 vpshufd \$78, $TMP1, $TMP3
107 vpxor $TMP3, $TMP2, $TMP1
110 vpshufd \$78, $TMP1, $TMP3
111 vpxor $TMP3, $TMP2, $TMP1
212 my $TMP3 = "%xmm6";
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dselect-bitext-bitwise-ops.ll8 ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
9 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
25 ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
26 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
42 ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
43 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
59 ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
60 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
76 ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
77 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
[all …]
Dselect-of-bittest.ll103 ; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
104 ; CHECK-NEXT: ret i32 [[TMP3]]
117 ; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
118 ; CHECK-NEXT: ret <2 x i32> [[TMP3]]
131 ; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
132 ; CHECK-NEXT: ret <2 x i32> [[TMP3]]
145 ; CHECK-NEXT: [[TMP3:%.*]] = zext <3 x i1> [[TMP2]] to <3 x i32>
146 ; CHECK-NEXT: ret <3 x i32> [[TMP3]]
163 ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
164 ; CHECK-NEXT: [[TMP5:%.*]] = zext i1 [[TMP3]] to i32
[all …]
Dor-shifted-masks.ll7 ; CHECK-NEXT: [[TMP3:%.*]] = shl i32 %x, 5
8 ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], 32
24 ; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 %x, 4
25 ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], 7
41 ; CHECK-NEXT: [[TMP3:%.*]] = shl i32 %x, 2
42 ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], 28
58 ; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 %x, 1
59 ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], 3
79 ; CHECK-NEXT: [[TMP3:%.*]] = shl i32 %x, 8
80 ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], 24576
[all …]
Dselect-obo-peo-ops.ll8 ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
9 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
25 ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
26 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
42 ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
43 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
59 ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
60 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
76 ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
77 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
[all …]
Dpow-4.ll51 ; CHECK-NEXT: [[TMP3:%.*]] = fmul fast <2 x float> [[TMP2]], [[TMP2]]
52 ; CHECK-NEXT: [[TMP4:%.*]] = fmul fast <2 x float> [[TMP1]], [[TMP3]]
65 ; CHECK-NEXT: [[TMP3:%.*]] = fmul fast <2 x double> [[SQUARE]], [[TMP2]]
66 … [[RECIPROCAL:%.*]] = fdiv fast <2 x double> <double 1.000000e+00, double 1.000000e+00>, [[TMP3]]
79 ; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP2]], [[TMP2]]
80 ; CHECK-NEXT: [[TMP4:%.*]] = fmul fast float [[SQUARE]], [[TMP3]]
105 ; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP2]], [[TMP2]]
106 ; CHECK-NEXT: [[TMP4:%.*]] = fmul fast float [[TMP3]], [[TMP3]]
130 ; CHECK-NEXT: [[TMP3:%.*]] = fmul fast double [[TMP2]], [[TMP2]]
131 ; CHECK-NEXT: [[TMP4:%.*]] = fmul fast double [[TMP3]], [[SQRT]]
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dlower-mem-intrinsics-threshold.ll26 ; OPT_NEG-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], [[LOADSTORELOOP]] ]
29 ; OPT_NEG-NEXT: [[TMP3]] = add i64 [[TMP1]], 1
30 ; OPT_NEG-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 0
51 ; OPT0-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], [[LOADSTORELOOP]] ]
54 ; OPT0-NEXT: [[TMP3]] = add i64 [[TMP1]], 1
55 ; OPT0-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 4
63 ; OPT_NEG-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], [[LOADSTORELOOP]] ]
66 ; OPT_NEG-NEXT: [[TMP3]] = add i64 [[TMP1]], 1
67 ; OPT_NEG-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 4
84 ; OPT4-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], [[LOADSTORELOOP]] ]
[all …]
Damdgpu-codegenprepare-i16-to-i32.ll14 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP1]], [[TMP2]]
15 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
33 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP1]], [[TMP2]]
34 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
52 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP1]], [[TMP2]]
53 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
71 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP1]], [[TMP2]]
72 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
90 ; VI-NEXT: [[TMP3:%.*]] = sub nsw i32 [[TMP1]], [[TMP2]]
91 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
[all …]
/external/llvm/test/Transforms/InstCombine/
Dand-or.ll7 ; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP1]], %b
8 ; CHECK-NEXT: ret i32 [[TMP3]]
20 ; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP1]], %b
21 ; CHECK-NEXT: ret i32 [[TMP3]]
33 ; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP1]], %b
34 ; CHECK-NEXT: ret i32 [[TMP3]]
46 ; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP1]], %b
47 ; CHECK-NEXT: ret i32 [[TMP3]]
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
Dzext.ll18 ; SSE2-NEXT: [[TMP3:%.*]] = zext <2 x i8> [[TMP2]] to <2 x i64>
19 ; SSE2-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i32 0
21 ; SSE2-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP3]], i32 1
39 ; AVX-NEXT: [[TMP3:%.*]] = zext <2 x i8> [[TMP2]] to <2 x i64>
40 ; AVX-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i32 0
42 ; AVX-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP3]], i32 1
63 ; SSE2-NEXT: [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i32>
64 ; SSE2-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i32 0
66 ; SSE2-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP3]], i32 1
68 ; SSE2-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP3]], i32 2
[all …]
Dsext.ll28 ; AVX-NEXT: [[TMP3:%.*]] = sext <2 x i8> [[TMP2]] to <2 x i64>
29 ; AVX-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i32 0
31 ; AVX-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP3]], i32 1
52 ; SSE2-NEXT: [[TMP3:%.*]] = sext <4 x i8> [[TMP2]] to <4 x i32>
53 ; SSE2-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i32 0
55 ; SSE2-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP3]], i32 1
57 ; SSE2-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP3]], i32 2
59 ; SSE2-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP3]], i32 3
87 ; AVX-NEXT: [[TMP3:%.*]] = sext <4 x i8> [[TMP2]] to <4 x i32>
88 ; AVX-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i32 0
[all …]
Dpr42022.ll15 ; CHECK-NEXT: [[TMP3:%.*]] = fadd fast <4 x float> [[TMP2]], <float 1.100000e+01, float 1.200000…
16 ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
18 ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i32 1
20 ; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP3]], i32 2
22 ; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP3]], i32 3
63 ; CHECK-NEXT: [[TMP3:%.*]] = fadd fast <4 x float> [[TMP2]], <float 1.100000e+01, float 1.200000…
64 ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
66 ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i32 1
68 ; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP3]], i32 2
70 ; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP3]], i32 3
[all …]
Dpr44067.ll12 ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
13 ; CHECK-NEXT: [[INS1:%.*]] = insertelement <2 x float> undef, float [[TMP3]], i32 1
46 ; CHECK-NEXT: [[TMP3:%.*]] = add <8 x i16> [[TMP2]], <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, …
47 ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i16> [[TMP3]], i32 1
49 ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i16> [[TMP3]], i32 0
51 ; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i16> [[TMP3]], i32 2
53 ; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i16> [[TMP3]], i32 3
55 ; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i16> [[TMP3]], i32 4
57 ; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i16> [[TMP3]], i32 5
59 ; CHECK-NEXT: [[TMP10:%.*]] = extractelement <8 x i16> [[TMP3]], i32 7
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/X86/
Dx86-addsub.ll15 ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP1:%.*]], <2 x double> undef, <2 x i…
16 ; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x double> [[TMP0:%.*]], [[TMP3]]
29 ; CHECK-NEXT: [[TMP3:%.*]] = fsub <2 x double> [[TMP0:%.*]], [[TMP1:%.*]]
30 ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0
42 ; CHECK-NEXT: [[TMP3:%.*]] = tail call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> [[TMP0:%…
43 ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
44 ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i32 1
59 ; CHECK-NEXT: [[TMP3:%.*]] = fadd <4 x float> [[TMP0:%.*]], [[TMP1:%.*]]
60 ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i32 1
61 ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i32 1
[all …]
/external/llvm-project/llvm/test/Instrumentation/PoisonChecking/
Dub-checks.ll14 ; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
15 ; CHECK-NEXT: call void @__poison_checker_assert(i1 [[TMP3]])
31 ; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
32 ; CHECK-NEXT: call void @__poison_checker_assert(i1 [[TMP3]])
48 ; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
49 ; CHECK-NEXT: call void @__poison_checker_assert(i1 [[TMP3]])
65 ; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
66 ; CHECK-NEXT: call void @__poison_checker_assert(i1 [[TMP3]])
81 ; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
82 ; CHECK-NEXT: call void @__poison_checker_assert(i1 [[TMP3]])
[all …]
Dbasic-flag-validation.ll20 ; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
21 ; CHECK-NEXT: call void @__poison_checker_assert(i1 [[TMP3]])
33 ; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
34 ; CHECK-NEXT: call void @__poison_checker_assert(i1 [[TMP3]])
45 ; CHECK-NEXT: [[TMP3:%.*]] = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 [[A]], i32 [[B]])
46 ; CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP3]], 1
71 ; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
72 ; CHECK-NEXT: call void @__poison_checker_assert(i1 [[TMP3]])
84 ; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
85 ; CHECK-NEXT: call void @__poison_checker_assert(i1 [[TMP3]])
[all …]
/external/llvm-project/llvm/test/Transforms/AtomicExpand/X86/
Dexpand-atomic-libcall.ll9 ; CHECK-NEXT: [[TMP3:%.*]] = bitcast i256* [[TMP2]] to i8*
10 ; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 32, i8* [[TMP3]])
11 ; CHECK-NEXT: call void @__atomic_load(i64 32, i8* [[TMP1]], i8* [[TMP3]], i32 0)
13 ; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 32, i8* [[TMP3]])
24 ; CHECK-NEXT: [[TMP3:%.*]] = alloca i256, align 8
25 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast i256* [[TMP3]] to i8*
28 ; CHECK-NEXT: [[TMP5:%.*]] = load i256, i256* [[TMP3]], align 8
/external/llvm-project/llvm/test/Transforms/AtomicExpand/AMDGPU/
Dexpand-atomic-rmw-nand.ll13 ; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg i32* [[PTR]], i32 [[LOADED]], i32 [[NEW]] seq_cst seq_cst
14 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP3]], 1
15 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP3]], 0
32 ; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg i32 addrspace(1)* [[PTR]], i32 [[LOADED]], i32 [[NEW]] seq_…
33 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP3]], 1
34 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP3]], 0
51 ; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg i32 addrspace(3)* [[PTR]], i32 [[LOADED]], i32 [[NEW]] seq_…
52 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP3]], 1
53 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP3]], 0
Dexpand-atomic-rmw-fadd.ll14 ; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
16 ; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst
31 ; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
33 ; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst
48 ; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
50 ; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst
70 ; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
72 ; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst…
87 ; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
89 ; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_c…
[all …]
Dunaligned-atomic.ll9 ; GCN-NEXT: [[TMP3:%.*]] = alloca i32, align 4
10 ; GCN-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP3]] to i8*
13 ; GCN-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP3]], align 4
25 ; GCN-NEXT: [[TMP3:%.*]] = alloca i32, align 4
26 ; GCN-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP3]] to i8*
28 ; GCN-NEXT: store i32 [[VAL:%.*]], i32* [[TMP3]], align 4
/external/llvm-project/llvm/test/Transforms/IndVarSimplify/
Dlftr-dead-ivs.ll29 …ptr inbounds ([240 x i8], [240 x i8]* @data, i64 0, i64 0), [[ENTRY]] ], [ [[TMP3:%.*]], [[CONT]] ]
30 ; CHECK-NEXT: [[TMP3]] = getelementptr inbounds i8, i8* [[P_0]], i64 1
33 ; CHECK-NEXT: store volatile i8 0, i8* [[TMP3]], align 1
72 ; CHECK-NEXT: [[P_0:%.*]] = phi i8* [ [[A:%.*]], [[ENTRY]] ], [ [[TMP3:%.*]], [[CONT]] ]
73 ; CHECK-NEXT: [[TMP3]] = getelementptr inbounds i8, i8* [[P_0]], i64 1
76 ; CHECK-NEXT: store volatile i8 0, i8* [[TMP3]], align 1
112 …inbounds ([240 x i8], [240 x i8]* @data, i64 0, i64 0), [[ENTRY:%.*]] ], [ [[TMP3:%.*]], [[LOOP]] ]
114 ; CHECK-NEXT: [[TMP3]] = getelementptr inbounds i8, i8* [[P_0]], i64 1
141 …inbounds ([240 x i8], [240 x i8]* @data, i64 0, i64 0), [[ENTRY:%.*]] ], [ [[TMP3:%.*]], [[LOOP]] ]
142 ; CHECK-NEXT: [[TMP3]] = getelementptr inbounds i8, i8* [[P_0]], i64 1
[all …]
/external/llvm-project/llvm/test/Transforms/Reassociate/
Dmulfactor.ll40 ; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP2]]
41 ; CHECK-NEXT: ret i32 [[TMP3]]
58 ; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[X]]
59 ; CHECK-NEXT: [[F:%.*]] = mul i32 [[TMP3]], [[TMP2]]
76 ; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP2]]
77 ; CHECK-NEXT: ret i32 [[TMP3]]
94 ; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[G]], [[TMP2]]
95 ; CHECK-NEXT: [[H:%.*]] = mul i32 [[TMP3]], [[Z:%.*]]
114 ; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[Z:%.*]]
115 ; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], [[Y]]
[all …]
/external/llvm-project/llvm/test/Transforms/CodeGenPrepare/PowerPC/
Dsplit-store-alignment.ll15 ; BE-NEXT: [[TMP3:%.*]] = bitcast i64* [[P]] to i32*
16 ; BE-NEXT: store i32 0, i32* [[TMP3]], align 1
28 ; LE-NEXT: [[TMP3:%.*]] = getelementptr i32, i32* [[TMP2]], i32 1
29 ; LE-NEXT: store i32 0, i32* [[TMP3]], align 1
51 ; BE-NEXT: [[TMP3:%.*]] = bitcast i64* [[P]] to i32*
52 ; BE-NEXT: store i32 0, i32* [[TMP3]], align 2
64 ; LE-NEXT: [[TMP3:%.*]] = getelementptr i32, i32* [[TMP2]], i32 1
65 ; LE-NEXT: store i32 0, i32* [[TMP3]], align 2
87 ; BE-NEXT: [[TMP3:%.*]] = bitcast i64* [[P]] to i32*
88 ; BE-NEXT: store i32 0, i32* [[TMP3]], align 8
[all …]
/external/llvm-project/llvm/test/Transforms/AggressiveInstCombine/
Dmasked-cmp.ll10 ; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
11 ; CHECK-NEXT: ret i32 [[TMP3]]
23 ; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
24 ; CHECK-NEXT: ret <2 x i32> [[TMP3]]
36 ; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
37 ; CHECK-NEXT: ret i32 [[TMP3]]
53 ; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
54 ; CHECK-NEXT: ret <2 x i32> [[TMP3]]
72 ; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
73 ; CHECK-NEXT: ret i32 [[TMP3]]
[all …]
/external/llvm-project/llvm/test/Transforms/Attributor/ArgumentPromotion/
Dpr32917.ll17 ; IS__TUNIT____-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to i32*
18 ; IS__TUNIT____-NEXT: call fastcc void @fn1(i32* nocapture nofree readonly align 4 [[TMP3]]) [[A…
26 ; IS__CGSCC____-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to i32*
27 …XT: call fastcc void @fn1(i32* nocapture nofree nonnull readonly align 4 [[TMP3]]) [[ATTR1:#.*]]
42 ; IS__TUNIT____-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
43 ; IS__TUNIT____-NEXT: store i32 [[TMP3]], i32* @a, align 4
50 ; IS__CGSCC____-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
51 ; IS__CGSCC____-NEXT: store i32 [[TMP3]], i32* @a, align 4

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