| /art/compiler/dex/quick/ |
| D | mir_to_lir-inl.h | 44 inline LIR* Mir2Lir::RawLIR(DexOffset dalvik_offset, int opcode, int op0, in RawLIR()
69 inline LIR* Mir2Lir::NewLIR0(int opcode) { in NewLIR0()
79 inline LIR* Mir2Lir::NewLIR1(int opcode, int dest) { in NewLIR1()
89 inline LIR* Mir2Lir::NewLIR2(int opcode, int dest, int src1) { in NewLIR2()
99 inline LIR* Mir2Lir::NewLIR2NoDest(int opcode, int src, int info) { in NewLIR2NoDest()
109 inline LIR* Mir2Lir::NewLIR3(int opcode, int dest, int src1, int src2) { in NewLIR3()
119 inline LIR* Mir2Lir::NewLIR4(int opcode, int dest, int src1, int src2, int info) { in NewLIR4()
129 inline LIR* Mir2Lir::NewLIR5(int opcode, int dest, int src1, int src2, int info1, in NewLIR5()
162 int opcode = lir->opcode; in SetupResourceMasks() local
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| D | mir_to_lir.cc | 393 Instruction::Code opcode = mir->dalvikInsn.opcode; in CompileDalvikInstruction() local
1166 int opcode = mir->dalvikInsn.opcode; in MethodBlockCodeGen() local
1266 LIR* Mir2Lir::LIRSlowPath::GenerateTargetLabel(int opcode) { in GenerateTargetLabel()
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| /art/compiler/dex/quick/x86/ |
| D | utility_x86.cc | 30 int opcode; in OpFpRegCopy() local
121 X86OpCode opcode = kX86Bkpt; in OpReg() local
134 X86OpCode opcode = kX86Bkpt; in OpRegImm() local
197 X86OpCode opcode = kX86Nop; in OpRegReg() local
253 X86OpCode opcode = kX86Nop; in OpMovRegMem() local
307 X86OpCode opcode = kX86Nop; in OpMovMemReg() local
366 X86OpCode opcode = kX86Nop; in OpRegMem() local
396 X86OpCode opcode = kX86Nop; in OpMemReg() local
424 X86OpCode opcode = kX86Nop; in OpRegMem() local
499 X86OpCode opcode = IS_SIMM8(value) ? kX86Imul32RRI8 : kX86Imul32RRI; in OpRegRegImm() local
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| D | fp_x86.cc | 24 void X86Mir2Lir::GenArithOpFloat(Instruction::Code opcode, in GenArithOpFloat()
75 void X86Mir2Lir::GenArithOpDouble(Instruction::Code opcode, in GenArithOpDouble()
159 int opcode = is_double ? kX86Fstp64M : kX86Fstp32M; in GenLongToFP() local
193 void X86Mir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest, in GenConversion()
419 int opcode = is_double ? kX86Fst64M : kX86Fst32M; in GenRemFP() local
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| D | target_x86.cc | 557 bool X86Mir2Lir::ProvidesFullMemoryBarrier(X86OpCode opcode) { in ProvidesFullMemoryBarrier()
894 uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) { in GetTargetInstFlags()
899 const char* X86Mir2Lir::GetTargetInstName(int opcode) { in GetTargetInstName()
904 const char* X86Mir2Lir::GetTargetInstFmt(int opcode) { in GetTargetInstFmt()
1803 void X86Mir2Lir::AppendOpcodeWithConst(X86OpCode opcode, int reg, MIR* mir) { in AppendOpcodeWithConst()
1883 int opcode = 0; in GenMultiplyVector() local
1913 int opcode = 0; in GenAddVector() local
1944 int opcode = 0; in GenSubtractVector() local
1974 int opcode = 0; in GenShiftByteVector() local
2024 int opcode = 0; in GenShiftLeftVector() local
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| /art/compiler/dex/ |
| D | local_value_numbering_test.cc | 44 Instruction::Code opcode; member
53 #define DEF_CONST(opcode, reg, value) \ argument
55 #define DEF_CONST_WIDE(opcode, reg, value) \ argument
57 #define DEF_CONST_STRING(opcode, reg, index) \ argument
59 #define DEF_IGET(opcode, reg, obj, field_info) \ argument
61 #define DEF_IGET_WIDE(opcode, reg, obj, field_info) \ argument
63 #define DEF_IPUT(opcode, reg, obj, field_info) \ argument
65 #define DEF_IPUT_WIDE(opcode, reg, obj, field_info) \ argument
67 #define DEF_SGET(opcode, reg, field_info) \ argument
69 #define DEF_SGET_WIDE(opcode, reg, field_info) \ argument
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| D | global_value_numbering_test.cc | 58 Instruction::Code opcode; member
90 #define DEF_CONST(bb, opcode, reg, value) \ argument
92 #define DEF_CONST_WIDE(bb, opcode, reg, value) \ argument
94 #define DEF_CONST_STRING(bb, opcode, reg, index) \ argument
96 #define DEF_IGET(bb, opcode, reg, obj, field_info) \ argument
98 #define DEF_IGET_WIDE(bb, opcode, reg, obj, field_info) \ argument
100 #define DEF_IPUT(bb, opcode, reg, obj, field_info) \ argument
102 #define DEF_IPUT_WIDE(bb, opcode, reg, obj, field_info) \ argument
104 #define DEF_SGET(bb, opcode, reg, field_info) \ argument
106 #define DEF_SGET_WIDE(bb, opcode, reg, field_info) \ argument
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| D | post_opt_passes.cc | 64 Instruction::Code opcode = mir->dalvikInsn.opcode; in Worker() local
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| D | mir_optimization.cc | 215 static constexpr bool IsInstructionIfCcZ(Instruction::Code opcode) { in IsInstructionIfCcZ()
219 static constexpr ConditionCode ConditionCodeForIfCcZ(Instruction::Code opcode) { in ConditionCodeForIfCcZ()
342 Instruction::Code opcode = mir->dalvikInsn.opcode; in BasicBlockOpt() local
633 Instruction::Code opcode = prev->last_mir_insn->dalvikInsn.opcode; in LayoutBlocks() local
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| /art/compiler/dex/quick/mips/ |
| D | utility_mips.cc | 26 int opcode; in OpFpRegCopy() local
117 MipsOpCode opcode = kMipsNop; in OpReg() local
136 MipsOpCode opcode = kMipsNop; in OpRegImm() local
162 MipsOpCode opcode = kMipsNop; in OpRegRegReg() local
204 MipsOpCode opcode = kMipsNop; in OpRegRegImm() local
286 MipsOpCode opcode = kMipsNop; in OpRegReg() local
360 MipsOpCode opcode = kMipsNop; in LoadBaseIndexed() local
412 MipsOpCode opcode = kMipsNop; in StoreBaseIndexed() local
468 MipsOpCode opcode = kMipsNop; in LoadBaseDispBody() local
579 MipsOpCode opcode = kMipsNop; in StoreBaseDispBody() local
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| D | fp_mips.cc | 24 void MipsMir2Lir::GenArithOpFloat(Instruction::Code opcode, in GenArithOpFloat()
70 void MipsMir2Lir::GenArithOpDouble(Instruction::Code opcode, in GenArithOpDouble()
116 void MipsMir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest, in GenConversion()
168 void MipsMir2Lir::GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, in GenCmpFP()
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| D | int_mips.cc | 395 void MipsMir2Lir::GenAddLong(Instruction::Code opcode, RegLocation rl_dest, in GenAddLong()
417 void MipsMir2Lir::GenSubLong(Instruction::Code opcode, RegLocation rl_dest, in GenSubLong()
439 void MipsMir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, in GenArithOpLong()
630 void MipsMir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, in GenShiftImmOpLong()
636 void MipsMir2Lir::GenArithImmOpLong(Instruction::Code opcode, in GenArithImmOpLong()
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| D | target_mips.cc | 590 uint64_t MipsMir2Lir::GetTargetInstFlags(int opcode) { in GetTargetInstFlags()
595 const char* MipsMir2Lir::GetTargetInstName(int opcode) { in GetTargetInstName()
600 const char* MipsMir2Lir::GetTargetInstFmt(int opcode) { in GetTargetInstFmt()
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| D | assemble_mips.cc | 41 #define ENCODING_MAP(opcode, skeleton, k0, ds, de, k1, s1s, s1e, k2, s2s, s2e, \ argument
463 int opcode = lir->opcode; in ConvertShortToLongBranch() local
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| /art/compiler/dex/quick/arm/ |
| D | utility_arm.cc | 224 ArmOpcode opcode = kThumbBkpt; in OpReg() local
242 ArmOpcode opcode = kThumbBkpt; in OpRegRegShift() local
392 ArmOpcode opcode = kThumbBkpt; in OpRegRegRegShift() local
467 ArmOpcode opcode = kThumbBkpt; in OpRegRegImm() local
604 ArmOpcode opcode = kThumbBkpt; in OpRegImm() local
696 ArmOpcode opcode = kThumbBkpt; in LoadBaseIndexed() local
762 ArmOpcode opcode = kThumbBkpt; in StoreBaseIndexed() local
824 LIR* ArmMir2Lir::LoadStoreUsingInsnWithOffsetImm8Shl2(ArmOpcode opcode, RegStorage r_base, in LoadStoreUsingInsnWithOffsetImm8Shl2()
857 ArmOpcode opcode = kThumbBkpt; in LoadBaseDispBody() local
998 ArmOpcode opcode = kThumbBkpt; in StoreBaseDispBody() local
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| D | fp_arm.cc | 23 void ArmMir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, in GenArithOpFloat()
69 void ArmMir2Lir::GenArithOpDouble(Instruction::Code opcode, in GenArithOpDouble()
116 void ArmMir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) { in GenConversion()
265 void ArmMir2Lir::GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, in GenCmpFP()
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| D | target_arm.cc | 167 int opcode = lir->opcode; in SetupTargetResourceMasks() local
297 static char* DecodeRegList(int opcode, int vector, char* buf, size_t buf_size) { in DecodeRegList()
736 uint64_t ArmMir2Lir::GetTargetInstFlags(int opcode) { in GetTargetInstFlags()
741 const char* ArmMir2Lir::GetTargetInstName(int opcode) { in GetTargetInstName()
746 const char* ArmMir2Lir::GetTargetInstFmt(int opcode) { in GetTargetInstFmt()
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| /art/compiler/dex/quick/arm64/ |
| D | utility_arm64.cc | 92 ArmOpcode opcode = UNWIDE(lir->opcode); in GetLoadStoreSize() local
334 bool Arm64Mir2Lir::InexpensiveConstantInt(int32_t value, Instruction::Code opcode) { in InexpensiveConstantInt()
418 ArmOpcode opcode = LIKELY(low_bits == 0) ? kA64Mov2rr : kA64Mvn2rr; in LoadConstantNoClobber() local
469 ArmOpcode opcode = LIKELY(value == 0) ? WIDE(kA64Mov2rr) : WIDE(kA64Mvn2rr); in LoadConstantWide() local
551 ArmOpcode opcode = kA64Brk1d; in OpReg() local
569 ArmOpcode opcode = kA64Brk1d; in OpRegRegShift() local
637 ArmOpcode opcode = kA64Brk1d; in OpRegRegExtend() local
697 ArmOpcode opcode = kA64Brk1d; in OpRegRegRegShift() local
765 ArmOpcode opcode = kA64Brk1d; in OpRegRegRegExtend() local
813 ArmOpcode opcode = kA64Brk1d; in OpRegRegImm64() local
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| D | assemble_arm64.cc | 60 #define ENCODING_MAP(opcode, variants, a0k, a0s, a0e, a1k, a1s, a1e, a2k, a2s, a2e, \ argument
655 ArmOpcode opcode = UNWIDE(lir->opcode); in EncodeLIRs() local
954 ArmOpcode opcode = UNWIDE(lir->opcode); in GetInsnSize() local
965 ArmOpcode opcode = UNWIDE(lir->opcode); in LinkFixupInsns() local
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| D | fp_arm64.cc | 24 void Arm64Mir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, in GenArithOpFloat()
66 void Arm64Mir2Lir::GenArithOpDouble(Instruction::Code opcode, in GenArithOpDouble()
119 void Arm64Mir2Lir::GenConversion(Instruction::Code opcode, in GenConversion()
251 void Arm64Mir2Lir::GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, in GenCmpFP()
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| D | int_arm64.cc | 63 void Arm64Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, in GenShiftOpLong()
103 int opcode; // The opcode. in GenSelect() local
207 int opcode = is_wide ? WIDE(kA64Csel4rrrc) : kA64Csel4rrrc; in GenSelect() local
265 ArmOpcode opcode = (arm_cond == kArmCondEq) ? kA64Cbz2rt : kA64Cbnz2rt; in OpCmpImmBranch() local
271 ArmOpcode opcode = kA64Cbz2rt; in OpCmpImmBranch() local
304 ArmOpcode opcode = kA64Brk1d; in OpRegCopyNoInsert() local
946 ArmOpcode opcode = reg.Is64Bit() ? WIDE(kA64Subs3rRd) : UNWIDE(kA64Subs3rRd); in OpDecAndBranch() local
1003 void Arm64Mir2Lir::GenDivRemLong(Instruction::Code opcode, RegLocation rl_dest, in GenDivRemLong()
1050 void Arm64Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, in GenArithOpLong()
1295 void Arm64Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, in GenShiftImmOpLong()
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| /art/runtime/quick/ |
| D | inline_method_analyser.h | 133 InlineMethodOpcode opcode; member
155 static constexpr bool IsInstructionIGet(Instruction::Code opcode) { in IsInstructionIGet()
159 static constexpr bool IsInstructionIPut(Instruction::Code opcode) { in IsInstructionIPut()
163 static constexpr uint16_t IGetVariant(Instruction::Code opcode) { in IGetVariant()
167 static constexpr uint16_t IPutVariant(Instruction::Code opcode) { in IPutVariant()
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| D | inline_method_analyser.cc | 97 Instruction::Code opcode = instruction->Opcode(); in AnalyseMethodCode() local
203 Instruction::Code opcode = instruction->Opcode(); in AnalyseIGetMethod() local
266 Instruction::Code opcode = instruction->Opcode(); in AnalyseIPutMethod() local
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| /art/runtime/ |
| D | dex_instruction.cc | 62 #define INSTRUCTION_SIZE(opcode, c, p, format, r, i, a, v) \ argument
92 Code opcode = static_cast<Code>(insn & 0xFF); in CanFlowThrough() local
138 const char* opcode = kInstructionNames[Opcode()]; in DumpString() local
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| D | dex_instruction.h | 86 #define INSTRUCTION_ENUM(opcode, cname, p, f, r, i, a, v) cname = opcode, argument
232 static const char* Name(Code opcode) { in Name()
408 void SetOpcode(Code opcode) { in SetOpcode()
439 static Format FormatOf(Code opcode) { in FormatOf()
444 static int FlagsOf(Code opcode) { in FlagsOf()
449 static int VerifyFlagsOf(Code opcode) { in VerifyFlagsOf()
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