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Searched refs:Arm64Mir2Lir (Results 1 – 7 of 7) sorted by relevance

/art/compiler/dex/quick/arm64/
Dtarget_arm64.cc85 RegLocation Arm64Mir2Lir::LocCReturn() { in LocCReturn()
89 RegLocation Arm64Mir2Lir::LocCReturnRef() { in LocCReturnRef()
93 RegLocation Arm64Mir2Lir::LocCReturnWide() { in LocCReturnWide()
97 RegLocation Arm64Mir2Lir::LocCReturnFloat() { in LocCReturnFloat()
101 RegLocation Arm64Mir2Lir::LocCReturnDouble() { in LocCReturnDouble()
106 RegStorage Arm64Mir2Lir::TargetReg(SpecialTargetRegister reg) { in TargetReg()
144 ResourceMask Arm64Mir2Lir::GetRegMaskCommon(const RegStorage& reg) const { in GetRegMaskCommon()
158 ResourceMask Arm64Mir2Lir::GetPCUseDefEncoding() const { in GetPCUseDefEncoding()
166 void Arm64Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, in SetupTargetResourceMasks()
188 ArmConditionCode Arm64Mir2Lir::ArmConditionEncoding(ConditionCode ccode) { in ArmConditionEncoding()
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Dutility_arm64.cc26 int32_t Arm64Mir2Lir::EncodeImmSingle(uint32_t bits) { in EncodeImmSingle()
58 int32_t Arm64Mir2Lir::EncodeImmDouble(uint64_t bits) { in EncodeImmDouble()
90 size_t Arm64Mir2Lir::GetLoadStoreSize(LIR* lir) { in GetLoadStoreSize()
99 size_t Arm64Mir2Lir::GetInstructionOffset(LIR* lir) { in GetInstructionOffset()
110 LIR* Arm64Mir2Lir::LoadFPConstantValue(RegStorage r_dest, int32_t value) { in LoadFPConstantValue()
134 LIR* Arm64Mir2Lir::LoadFPConstantValueWide(RegStorage r_dest, int64_t value) { in LoadFPConstantValueWide()
182 int Arm64Mir2Lir::EncodeLogicalImmediate(bool is_wide, uint64_t value) { in EncodeLogicalImmediate()
309 bool Arm64Mir2Lir::InexpensiveConstantInt(int32_t value) { in InexpensiveConstantInt()
315 bool Arm64Mir2Lir::InexpensiveConstantFloat(int32_t value) { in InexpensiveConstantFloat()
319 bool Arm64Mir2Lir::InexpensiveConstantLong(int64_t value) { in InexpensiveConstantLong()
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Dint_arm64.cc29 LIR* Arm64Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
34 LIR* Arm64Mir2Lir::OpIT(ConditionCode ccode, const char* guide) { in OpIT()
39 void Arm64Mir2Lir::OpEndIT(LIR* it) { in OpEndIT()
49 void Arm64Mir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, in GenCmpLong()
63 void Arm64Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, in GenShiftOpLong()
91 void Arm64Mir2Lir::GenSelect(int32_t true_val, int32_t false_val, ConditionCode ccode, in GenSelect()
175 void Arm64Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32()
183 void Arm64Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { in GenSelect()
214 void Arm64Mir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { in GenFusedLongCmpBranch()
259 LIR* Arm64Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, in OpCmpImmBranch()
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Dfp_arm64.cc24 void Arm64Mir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, in GenArithOpFloat()
66 void Arm64Mir2Lir::GenArithOpDouble(Instruction::Code opcode, in GenArithOpDouble()
119 void Arm64Mir2Lir::GenConversion(Instruction::Code opcode, in GenConversion()
201 void Arm64Mir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, in GenFusedFPCmpBranch()
251 void Arm64Mir2Lir::GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, in GenCmpFP()
309 void Arm64Mir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src) { in GenNegFloat()
317 void Arm64Mir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src) { in GenNegDouble()
344 bool Arm64Mir2Lir::GenInlinedAbsFloat(CallInfo* info) { in GenInlinedAbsFloat()
362 bool Arm64Mir2Lir::GenInlinedAbsDouble(CallInfo* info) { in GenInlinedAbsDouble()
380 bool Arm64Mir2Lir::GenInlinedSqrt(CallInfo* info) { in GenInlinedSqrt()
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Dcall_arm64.cc46 void Arm64Mir2Lir::GenLargeSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) { in GenLargeSparseSwitch()
98 void Arm64Mir2Lir::GenLargePackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) { in GenLargePackedSwitch()
159 void Arm64Mir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src) { in GenFillArrayData()
188 void Arm64Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) { in GenMonitorEnter()
237 void Arm64Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) { in GenMonitorExit()
279 void Arm64Mir2Lir::GenMoveException(RegLocation rl_dest) { in GenMoveException()
290 void Arm64Mir2Lir::MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) { in MarkGCCard()
305 void Arm64Mir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) { in GenEntrySequence()
416 void Arm64Mir2Lir::GenExitSequence() { in GenExitSequence()
432 void Arm64Mir2Lir::GenSpecialExitSequence() { in GenSpecialExitSequence()
Dassemble_arm64.cc105 const ArmEncodingMap Arm64Mir2Lir::EncodingMap[kA64Last] = {
628 void Arm64Mir2Lir::ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir) { in ReplaceFixup()
639 void Arm64Mir2Lir::InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir) { in InsertFixupBefore()
652 uint8_t* Arm64Mir2Lir::EncodeLIRs(uint8_t* write_pos, LIR* lir) { in EncodeLIRs()
814 void Arm64Mir2Lir::AssembleLIR() { in AssembleLIR()
953 size_t Arm64Mir2Lir::GetInsnSize(LIR* lir) { in GetInsnSize()
960 uint32_t Arm64Mir2Lir::LinkFixupInsns(LIR* head_lir, LIR* tail_lir, uint32_t offset) { in LinkFixupInsns()
993 void Arm64Mir2Lir::AssignDataOffsets() { in AssignDataOffsets()
Dcodegen_arm64.h27 class Arm64Mir2Lir FINAL : public Mir2Lir {
63 Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);