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Searched refs:OpRegRegReg (Results 1 – 17 of 17) sorted by relevance

/art/compiler/dex/quick/mips/
Dint_mips.cc347 OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, t_reg); in GenMultiplyByTwoBitMultiplier()
357 OpRegRegReg(kOpOr, t_reg, reg.GetLow(), reg.GetHigh()); in GenDivZeroCheckWide()
408 OpRegRegReg(kOpAdd, rl_result.reg.GetLow(), rl_src2.reg.GetLow(), rl_src1.reg.GetLow()); in GenAddLong()
410 OpRegRegReg(kOpAdd, t_reg, rl_src2.reg.GetHigh(), rl_src1.reg.GetHigh()); in GenAddLong()
412 OpRegRegReg(kOpAdd, rl_result.reg.GetHigh(), rl_result.reg.GetHigh(), t_reg); in GenAddLong()
432 OpRegRegReg(kOpSub, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); in GenSubLong()
433 OpRegRegReg(kOpSub, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); in GenSubLong()
434 OpRegRegReg(kOpSub, rl_result.reg.GetHigh(), rl_result.reg.GetHigh(), t_reg); in GenSubLong()
477 OpRegRegReg(kOpSub, rl_result.reg.GetHigh(), rl_result.reg.GetHigh(), t_reg); in GenNegLong()
Dcall_mips.cc106 OpRegRegReg(kOpAdd, r_end, r_end, r_base); in GenLargeSparseSwitch()
120 OpRegRegReg(kOpAdd, rs_rRA, rs_rRA, r_disp); in GenLargeSparseSwitch()
181 OpRegRegReg(kOpSub, r_key, rl_src.reg, r_key); in GenLargePackedSwitch()
205 OpRegRegReg(kOpAdd, rs_rRA, rs_rRA, r_disp); in GenLargePackedSwitch()
Dutility_mips.cc161 LIR* MipsMir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) { in OpRegRegReg() function in art::MipsMir2Lir
302 return OpRegRegReg(op, r_dest_src1, r_dest_src1, r_src2); in OpRegReg()
Dcodegen_mips.h155 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
/art/compiler/dex/quick/arm/
Dint_arm.cc132 OpRegRegReg(kOpSub, t_reg, rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); in GenCmpLong()
215 OpRegRegReg(kOpSub, rs_dest, left_op, right_op); in GenSelectConst32()
544 OpRegRegReg(kOpSub, rl_result.reg, rl_src.reg, tmp1); in SmallLiteralDivRem()
714 OpRegRegReg(kOpDiv, rl_result.reg, reg1, reg2); in GenDivRem()
722 OpRegRegReg(kOpDiv, temp, reg1, reg2); in GenDivRem()
724 OpRegRegReg(kOpSub, rl_result.reg, reg1, temp); in GenDivRem()
869 OpRegRegReg(kOpAdd, r_ptr, rl_object.reg, rl_offset.reg); in GenInlinedCas()
1154 OpRegRegReg(kOpSub, rl_result.reg.GetLow(), z_reg, rl_src.reg.GetLow()); in GenNegLong()
1155 OpRegRegReg(kOpSbc, rl_result.reg.GetHigh(), z_reg, t_reg); in GenNegLong()
1158 OpRegRegReg(kOpSub, rl_result.reg.GetLow(), z_reg, rl_src.reg.GetLow()); in GenNegLong()
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Dutility_arm.cc459 LIR* ArmMir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) { in OpRegRegReg() function in art::ArmMir2Lir
725 OpRegRegReg(kOpAdd, reg_ptr, r_base, r_index); in LoadBaseIndexed()
792 OpRegRegReg(kOpAdd, reg_ptr, r_base, r_index); in StoreBaseIndexed()
Dcodegen_arm.h158 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
/art/compiler/dex/quick/
Dgen_common.cc1370 OpRegRegReg(first_op, t_reg, rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); in GenLong3Addr()
1371 OpRegRegReg(second_op, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); in GenLong3Addr()
1375 OpRegRegReg(first_op, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); in GenLong3Addr()
1376 OpRegRegReg(second_op, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); in GenLong3Addr()
1506 OpRegRegReg(op, rl_result.reg, rl_src1.reg, t_reg); in GenArithOpInt()
1512 OpRegRegReg(op, rl_result.reg, rl_src1.reg, rl_src2.reg); in GenArithOpInt()
1595 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg); in HandleEasyDivRem()
1600 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg); in HandleEasyDivRem()
1608 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg); in HandleEasyDivRem()
1610 OpRegRegReg(kOpSub, rl_result.reg, t_reg2, t_reg1); in HandleEasyDivRem()
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Dgen_invoke.cc1202 LIR* or_inst = OpRegRegReg(kOpOr, reg_slow_path, reg_slow_path, reg_disabled); in GenInlinedReferenceGetReferent()
1314 OpRegRegReg(kOpAdc, rl_result.reg, rl_result.reg, t_reg); in GenInlinedStringIsEmptyOrLength()
1376 OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, sign_reg); in GenInlinedAbsInt()
1412 OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, sign_reg); in GenInlinedAbsLong()
1417 OpRegRegReg(kOpAdd, rl_result.reg.GetLow(), rl_src.reg.GetLow(), sign_reg); in GenInlinedAbsLong()
1418 OpRegRegReg(kOpAdc, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), sign_reg); in GenInlinedAbsLong()
1623 OpRegRegReg(kOpAdd, rl_temp_offset, rl_object.reg, rl_offset.reg); in GenInlinedUnsafeGet()
1671 OpRegRegReg(kOpAdd, rl_temp_offset, rl_object.reg, rl_offset.reg); in GenInlinedUnsafePut()
Dmir_to_lir.h1437 virtual LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1,
/art/compiler/dex/quick/arm64/
Dint_arm64.cc85 OpRegRegReg(op, rl_result.reg, rl_src1.reg, As64BitReg(rl_shift.reg)); in GenShiftOpLong()
501 OpRegRegReg(kOpAdd, r_long_mul, rl_src.reg, r_long_mul); in SmallLiteralDivRem64()
623 OpRegRegReg(kOpDiv, rl_result.reg, r_src1, r_src2); in GenDivRem()
636 OpRegRegReg(kOpDiv, temp, r_src1, r_src2); in GenDivRem()
652 OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, sign_reg); in GenInlinedAbsLong()
736 OpRegRegReg(kOpAdd, r_ptr, rl_object.reg, rl_offset.reg); in GenInlinedCas()
Dcodegen_arm64.h223 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE;
Dutility_arm64.cc801 LIR* Arm64Mir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) { in OpRegRegReg() function in art::Arm64Mir2Lir
/art/compiler/dex/quick/x86/
Dint_x86.cc486 OpRegRegReg(kOpOr, t_reg, low_reg, high_reg); in GenFusedLongCmpImmBranch()
1113 OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, t_reg); in GenMultiplyByTwoBitMultiplier()
1131 OpRegRegReg(kOpOr, t_reg, reg.GetLow(), reg.GetHigh()); in GenDivZeroCheckWide()
2836 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, t_reg); in GenArithOpInt()
2875 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); in GenArithOpInt()
2887 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); in GenArithOpInt()
2918 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); in GenArithOpInt()
2925 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); in GenArithOpInt()
3020 OpRegRegReg(op, rl_result.reg, rl_src1.reg, t_reg); in GenShiftOpLong()
Dcodegen_x86.h282 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE;
Dutility_x86.cc445 LIR* X86Mir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, in OpRegRegReg() function in art::X86Mir2Lir
Dtarget_x86.cc1139 OpRegRegReg(kOpSub, tmp_reg, rs_rAX, tmp_reg); in GenInlinedArrayCopyCharArray()
1164 OpRegRegReg(kOpSub, tmp_reg, rs_rAX, tmp_reg); in GenInlinedArrayCopyCharArray()