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Searched refs:OpSize (Results 1 – 22 of 22) sorted by relevance

/art/compiler/dex/quick/mips/
Dcodegen_mips.h36 OpSize size, VolatileKind is_volatile) OVERRIDE;
38 OpSize size) OVERRIDE;
42 OpSize size, VolatileKind is_volatile) OVERRIDE;
44 OpSize size) OVERRIDE;
84 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
89 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
91 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
107 bool GenInlinedPeek(CallInfo* info, OpSize size);
108 bool GenInlinedPoke(CallInfo* info, OpSize size);
163 OpSize size);
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Dutility_mips.cc357 int scale, OpSize size) { in LoadBaseIndexed()
410 int scale, OpSize size) { in StoreBaseIndexed()
456 OpSize size) { in LoadBaseDispBody()
553 OpSize size, VolatileKind is_volatile) { in LoadBaseDisp()
575 RegStorage r_src, OpSize size) { in StoreBaseDispBody()
656 OpSize size, VolatileKind is_volatile) { in StoreBaseDisp()
Dint_mips.cc296 bool MipsMir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { in GenInlinedPeek()
312 bool MipsMir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { in GenInlinedPoke()
485 void MipsMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, in GenArrayGet()
554 void MipsMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, in GenArrayPut()
Dtarget_mips.cc562 RegisterClass MipsMir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { in RegClassForFieldLoadStore()
/art/compiler/dex/quick/arm/
Dcodegen_arm.h36 OpSize size, VolatileKind is_volatile) OVERRIDE;
38 OpSize size) OVERRIDE;
42 OpSize size, VolatileKind is_volatile) OVERRIDE;
44 OpSize size) OVERRIDE;
84 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
91 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
93 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
109 bool GenInlinedPeek(CallInfo* info, OpSize size);
110 bool GenInlinedPoke(CallInfo* info, OpSize size);
164 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size);
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Dutility_arm.cc693 int scale, OpSize size) { in LoadBaseIndexed()
759 int scale, OpSize size) { in StoreBaseIndexed()
855 OpSize size) { in LoadBaseDispBody()
966 OpSize size, VolatileKind is_volatile) { in LoadBaseDisp()
996 OpSize size) { in StoreBaseDispBody()
1088 OpSize size, VolatileKind is_volatile) { in StoreBaseDisp()
Dint_arm.cc751 bool ArmMir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { in GenInlinedPeek()
776 bool ArmMir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { in GenInlinedPoke()
1293 void ArmMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, in GenArrayGet()
1381 void ArmMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, in GenArrayPut()
Dtarget_arm.cc541 RegisterClass ArmMir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { in RegClassForFieldLoadStore()
/art/compiler/dex/quick/arm64/
Dcodegen_arm64.h76 OpSize size, VolatileKind is_volatile) OVERRIDE;
80 OpSize size) OVERRIDE;
85 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,
90 OpSize size) OVERRIDE;
137 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
144 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
146 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
157 bool GenInlinedReverseBits(CallInfo* info, OpSize size) OVERRIDE;
168 bool GenInlinedPeek(CallInfo* info, OpSize size) OVERRIDE;
169 bool GenInlinedPoke(CallInfo* info, OpSize size) OVERRIDE;
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Dutility_arm64.cc1025 int scale, OpSize size) { in LoadBaseIndexed()
1113 int scale, OpSize size) { in StoreBaseIndexed()
1198 OpSize size) { in LoadBaseDispBody()
1275 OpSize size, VolatileKind is_volatile) { in LoadBaseDisp()
1295 OpSize size) { in StoreBaseDispBody()
1366 OpSize size, VolatileKind is_volatile) { in StoreBaseDisp()
Dtarget_arm64.cc570 RegisterClass Arm64Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { in RegClassForFieldLoadStore()
859 OpSize* op_size) { in GetArgPhysicalReg()
940 OpSize op_size; in FlushIns()
Dint_arm64.cc673 bool Arm64Mir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { in GenInlinedPeek()
689 bool Arm64Mir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { in GenInlinedPoke()
1101 void Arm64Mir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, in GenArrayGet()
1198 void Arm64Mir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, in GenArrayPut()
1688 bool Arm64Mir2Lir::GenInlinedReverseBits(CallInfo* info, OpSize size) { in GenInlinedReverseBits()
/art/compiler/dex/quick/x86/
Dcodegen_x86.h73 OpSize size, VolatileKind is_volatile) OVERRIDE;
75 OpSize size) OVERRIDE;
79 OpSize size, VolatileKind is_volatile) OVERRIDE;
81 OpSize size) OVERRIDE;
143 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
146 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
148 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
165 bool GenInlinedPeek(CallInfo* info, OpSize size) OVERRIDE;
166 bool GenInlinedPoke(CallInfo* info, OpSize size) OVERRIDE;
411 RegStorage r_dest, OpSize size);
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Dtarget_x86.cc698 OpSize size = cu_->target64 ? k64 : k32; in SpillCoreRegs()
715 OpSize size = cu_->target64 ? k64 : k32; in UnSpillCoreRegs()
759 RegisterClass X86Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { in RegClassForFieldLoadStore()
1880 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenMultiplyVector()
1910 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenAddVector()
1941 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenSubtractVector()
2021 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenShiftLeftVector()
2049 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenSignedShiftRightVector()
2074 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenUnsignedShiftRightVector()
2143 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenAddReduceVector()
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Dutility_x86.cc635 int displacement, RegStorage r_dest, OpSize size) { in LoadBaseIndexedDisp()
762 int scale, OpSize size) { in LoadBaseIndexed()
767 OpSize size, VolatileKind is_volatile) { in LoadBaseDisp()
782 int displacement, RegStorage r_src, OpSize size) { in StoreBaseIndexedDisp()
866 int scale, OpSize size) { in StoreBaseIndexed()
870 LIR* X86Mir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, in StoreBaseDisp()
Dint_x86.cc849 bool X86Mir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { in GenInlinedPeek()
871 bool X86Mir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { in GenInlinedPoke()
2061 void X86Mir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, in GenArrayGet()
2110 void X86Mir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, in GenArrayPut()
/art/compiler/dex/quick/
Dmir_to_lir.h592 RegisterClass RegClassBySize(OpSize size) { in RegClassBySize()
855 void GenIGet(MIR* mir, int opt_flags, OpSize size,
857 void GenIPut(MIR* mir, int opt_flags, OpSize size,
964 virtual bool GenInlinedReverseBits(CallInfo* info, OpSize size);
965 bool GenInlinedReverseBytes(CallInfo* info, OpSize size);
1150 OpSize size, VolatileKind is_volatile) = 0;
1152 int scale, OpSize size) = 0;
1156 OpSize size, VolatileKind is_volatile) = 0;
1158 int scale, OpSize size) = 0;
1255 virtual RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) = 0;
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Ddex_file_method_inliner.cc443 return backend->GenInlinedReverseBytes(info, static_cast<OpSize>(intrinsic.d.data)); in GenIntrinsic()
445 return backend->GenInlinedReverseBits(info, static_cast<OpSize>(intrinsic.d.data)); in GenIntrinsic()
488 return backend->GenInlinedPeek(info, static_cast<OpSize>(intrinsic.d.data)); in GenIntrinsic()
490 return backend->GenInlinedPoke(info, static_cast<OpSize>(intrinsic.d.data)); in GenIntrinsic()
Dgen_common.cc535 OpSize store_size = LoadStoreOpSize(is_long_or_double, is_object); in GenSput()
624 OpSize load_size = LoadStoreOpSize(is_long_or_double, is_object); in GenSget()
722 void Mir2Lir::GenIGet(MIR* mir, int opt_flags, OpSize size, in GenIGet()
727 OpSize load_size = LoadStoreOpSize(is_long_or_double, is_object); in GenIGet()
769 void Mir2Lir::GenIPut(MIR* mir, int opt_flags, OpSize size, in GenIPut()
774 OpSize store_size = LoadStoreOpSize(is_long_or_double, is_object); in GenIPut()
Dmir_to_lir.cc238 OpSize size = LoadStoreOpSize(wide, ref); in GenSpecialIGet()
282 OpSize size = LoadStoreOpSize(wide, ref); in GenSpecialIPut()
Dgen_invoke.cc1328 bool Mir2Lir::GenInlinedReverseBytes(CallInfo* info, OpSize size) { in GenInlinedReverseBytes()
1427 bool Mir2Lir::GenInlinedReverseBits(CallInfo* info, OpSize size) { in GenInlinedReverseBits()
/art/compiler/dex/
Dcompiler_enums.h262 enum OpSize { enum
275 std::ostream& operator<<(std::ostream& os, const OpSize& kind);