| /art/compiler/utils/mips64/ |
| D | assembler_mips64.h | 55 void Add(GpuRegister rd, GpuRegister rs, GpuRegister rt);
56 void Addi(GpuRegister rt, GpuRegister rs, uint16_t imm16);
57 void Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
58 void Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
59 void Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
60 void Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64
61 void Sub(GpuRegister rd, GpuRegister rs, GpuRegister rt);
62 void Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
63 void Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
65 void MultR2(GpuRegister rs, GpuRegister rt); // R2
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| D | assembler_mips64.cc | 33 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, in EmitR() argument
35 CHECK_NE(rs, kNoGpuRegister); in EmitR()
39 static_cast<uint32_t>(rs) << kRsShift | in EmitR()
47 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { in EmitI() argument
48 CHECK_NE(rs, kNoGpuRegister); in EmitI()
51 static_cast<uint32_t>(rs) << kRsShift | in EmitI()
57 void Mips64Assembler::EmitI21(int opcode, GpuRegister rs, uint32_t imm21) { in EmitI21() argument
58 CHECK_NE(rs, kNoGpuRegister); in EmitI21()
60 static_cast<uint32_t>(rs) << kRsShift | in EmitI21()
94 void Mips64Assembler::Add(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Add() argument
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| /art/compiler/utils/mips/ |
| D | assembler_mips.h | 58 void Add(Register rd, Register rs, Register rt);
59 void Addu(Register rd, Register rs, Register rt);
60 void Addi(Register rt, Register rs, uint16_t imm16);
61 void Addiu(Register rt, Register rs, uint16_t imm16);
62 void Sub(Register rd, Register rs, Register rt);
63 void Subu(Register rd, Register rs, Register rt);
64 void Mult(Register rs, Register rt);
65 void Multu(Register rs, Register rt);
66 void Div(Register rs, Register rt);
67 void Divu(Register rs, Register rt);
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| D | assembler_mips.cc | 42 void MipsAssembler::EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct) { in EmitR() argument
43 CHECK_NE(rs, kNoRegister); in EmitR()
47 static_cast<int32_t>(rs) << kRsShift | in EmitR()
55 void MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { in EmitI() argument
56 CHECK_NE(rs, kNoRegister); in EmitI()
59 static_cast<int32_t>(rs) << kRsShift | in EmitI()
93 void MipsAssembler::EmitBranch(Register rt, Register rs, Label* label, bool equal) { in EmitBranch() argument
103 Beq(rt, rs, (offset >> 2) & kBranchOffsetMask); in EmitBranch()
105 Bne(rt, rs, (offset >> 2) & kBranchOffsetMask); in EmitBranch()
163 void MipsAssembler::Add(Register rd, Register rs, Register rt) { in Add() argument
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| /art/disassembler/ |
| D | disassembler_mips.cc | 323 uint32_t rs = (instruction >> 21) & 0x1f; // I-type, R-type. in Dump() local
396 args << StringPrintf("%+d(r%d)", offset, rs); in Dump()
397 if (rs == 17) { in Dump()
407 case 'S': args << 'r' << rs; break; in Dump()
408 case 's': args << 'f' << rs; break; in Dump()
429 if (((op == 0x36 && rs == 0 && rt != 0) || // jic in Dump()
430 (op == 0x19 && rs == rt && rt != 0)) && // daddiu in Dump()
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| /art/compiler/dex/quick/arm64/ |
| D | arm64_lir.h | 103 #define A64_REGSTORAGE_IS_SP_OR_ZR(rs) (((rs).GetRegNum() & 0x1f) == 0x1f) argument
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| /art/compiler/dex/quick/ |
| D | mir_to_lir-inl.h | 274 inline void Mir2Lir::CheckRegStorage(RegStorage rs, WidenessCheck wide, RefCheck ref, FPCheck fp) in CheckRegStorage() argument
277 CheckRegStorageImpl(rs, wide, ref, fp, kFailOnSizeError, kReportSizeError); in CheckRegStorage()
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| D | mir_to_lir.cc | 1364 void Mir2Lir::CheckRegStorageImpl(RegStorage rs, WidenessCheck wide, RefCheck ref, FPCheck fp, in CheckRegStorageImpl() argument
1367 if (rs.Valid()) { in CheckRegStorageImpl()
1369 if (cu_->target64 && !rs.Is64Bit()) { in CheckRegStorageImpl()
1378 if (!rs.Is64Bit()) { in CheckRegStorageImpl()
1388 if (!rs.IsFloat()) { in CheckRegStorageImpl()
1396 if (rs.IsFloat()) { in CheckRegStorageImpl()
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| D | ralloc_util.cc | 647 RegStorage rs = reg.IsPair() ? reg.GetLow() : reg; in NullifyRange() local
648 if (IsTemp(rs)) { in NullifyRange()
707 RegStorage rs = rl.reg.IsPair() ? rl.reg.GetLow() : rl.reg; in ResetDefLocWide() local
708 if (IsTemp(rs) && !(cu_->disable_opt & (1 << kSuppressLoads))) { in ResetDefLocWide()
709 NullifyRange(rs, rl.s_reg_low); in ResetDefLocWide()
711 ResetDef(rs); in ResetDefLocWide()
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| D | mir_to_lir.h | 1741 void CheckRegStorageImpl(RegStorage rs, WidenessCheck wide, RefCheck ref, FPCheck fp, bool fail,
1753 void CheckRegStorage(RegStorage rs, WidenessCheck wide, RefCheck ref, FPCheck fp) const;
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| /art/compiler/utils/arm/ |
| D | assembler_arm.h | 60 ShifterOperand(Register rm, Shift shift, Register rs) : type_(kRegister), rm_(rm), in ShifterOperand() argument
61 rs_(rs), in ShifterOperand()
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| D | assembler_arm32.cc | 765 Register rm, Register rs) { in EmitMulOp() argument
769 CHECK_NE(rs, kNoRegister); in EmitMulOp()
775 (static_cast<int32_t>(rs) << kRsShift) | in EmitMulOp()
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| D | assembler_arm32.h | 338 Register rs);
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| D | assembler_thumb2.h | 405 Register rs);
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