Home
last modified time | relevance | path

Searched refs:CreateReg (Results 1 – 25 of 73) sorted by relevance

123

/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp533 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
536 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
572 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
575 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
614 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch()
617 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch()
658 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzlGroupBranch()
661 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzlGroupBranch()
706 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzGroupBranch()
710 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzGroupBranch()
[all …]
/external/llvm/lib/Target/X86/Disassembler/
DX86Disassembler.cpp183 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum)); in translateRegister()
251 MCOperand baseReg = MCOperand::CreateReg(baseRegNo); in translateSrcIndex()
255 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]); in translateSrcIndex()
276 MCOperand baseReg = MCOperand::CreateReg(baseRegNo); in translateDstIndex()
542 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
545 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4))); in translateImmediate()
548 mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4))); in translateImmediate()
576 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]); in translateImmediate()
609 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break; in translateRMRegister()
654 baseReg = MCOperand::CreateReg(X86::x); break; in translateRMMemory()
[all …]
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp700 TmpInst.addOperand(MCOperand::CreateReg(Mips::GP)); in emitDirectiveCpLoad()
709 TmpInst.addOperand(MCOperand::CreateReg(Mips::GP)); in emitDirectiveCpLoad()
710 TmpInst.addOperand(MCOperand::CreateReg(Mips::GP)); in emitDirectiveCpLoad()
719 TmpInst.addOperand(MCOperand::CreateReg(Mips::GP)); in emitDirectiveCpLoad()
720 TmpInst.addOperand(MCOperand::CreateReg(Mips::GP)); in emitDirectiveCpLoad()
721 TmpInst.addOperand(MCOperand::CreateReg(RegNo)); in emitDirectiveCpLoad()
742 Inst.addOperand(MCOperand::CreateReg(RegOrOffset)); in emitDirectiveCpsetup()
743 Inst.addOperand(MCOperand::CreateReg(Mips::GP)); in emitDirectiveCpsetup()
744 Inst.addOperand(MCOperand::CreateReg(Mips::ZERO)); in emitDirectiveCpsetup()
748 Inst.addOperand(MCOperand::CreateReg(Mips::GP)); in emitDirectiveCpsetup()
[all …]
DMipsNaClELFStreamer.cpp97 MaskInst.addOperand(MCOperand::CreateReg(AddrReg)); in emitMask()
98 MaskInst.addOperand(MCOperand::CreateReg(AddrReg)); in emitMask()
99 MaskInst.addOperand(MCOperand::CreateReg(MaskReg)); in emitMask()
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp529 static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, RegKind RegKind, in CreateReg() function in __anond0efcad40311::MipsOperand
705 Inst.addOperand(MCOperand::CreateReg(getGPR32Reg())); in addGPR32AsmRegOperands()
710 Inst.addOperand(MCOperand::CreateReg(getGPRMM16Reg())); in addGPRMM16AsmRegOperands()
715 Inst.addOperand(MCOperand::CreateReg(getGPRMM16Reg())); in addGPRMM16AsmRegZeroOperands()
720 Inst.addOperand(MCOperand::CreateReg(getGPRMM16Reg())); in addGPRMM16AsmRegMovePOperands()
728 Inst.addOperand(MCOperand::CreateReg(getGPR64Reg())); in addGPR64AsmRegOperands()
733 Inst.addOperand(MCOperand::CreateReg(getAFGR64Reg())); in addAFGR64AsmRegOperands()
738 Inst.addOperand(MCOperand::CreateReg(getFGR64Reg())); in addFGR64AsmRegOperands()
743 Inst.addOperand(MCOperand::CreateReg(getFGR32Reg())); in addFGR32AsmRegOperands()
752 Inst.addOperand(MCOperand::CreateReg(getFGRH32Reg())); in addFGRH32AsmRegOperands()
[all …]
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp1764 Inst.addOperand(MCOperand::CreateReg(RegNum)); in addCondCodeOperands()
1794 Inst.addOperand(MCOperand::CreateReg(getReg())); in addCCOutOperands()
1799 Inst.addOperand(MCOperand::CreateReg(getReg())); in addRegOperands()
1806 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); in addRegShiftedRegOperands()
1807 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
1816 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); in addRegShiftedImmOperands()
1834 Inst.addOperand(MCOperand::CreateReg(*I)); in addRegListOperands()
2043 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addMemNoOffsetOperands()
2070 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addAlignedMemoryOperands()
2133 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addAddrMode2Operands()
[all …]
/external/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp55 Inst.addOperand(MCOperand::CreateReg(RegNo)); in decodeRegisterClass()
192 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
202 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
213 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
215 Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr12Operand()
225 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr20Operand()
227 Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr20Operand()
237 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); in decodeBDLAddr12Len8Operand()
/external/llvm/lib/Target/Hexagon/Disassembler/
DHexagonDisassembler.cpp72 Inst.addOperand(MCOperand::CreateReg(Table[RegNo])); in DecodeRegisterClass()
86 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeIntRegsRegisterClass()
106 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeCtrRegsRegisterClass()
130 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeCtrRegs64RegisterClass()
147 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeModRegsRegisterClass()
172 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodePredRegsRegisterClass()
/external/llvm/lib/Target/X86/AsmParser/
DX86Operand.h367 Inst.addOperand(MCOperand::CreateReg(getReg())); in addRegOperands()
398 Inst.addOperand(MCOperand::CreateReg(RegNo)); in addGR32orGR64Operands()
411 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg())); in addMemOperands()
413 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg())); in addMemOperands()
415 Inst.addOperand(MCOperand::CreateReg(getMemSegReg())); in addMemOperands()
429 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg())); in addSrcIdxOperands()
430 Inst.addOperand(MCOperand::CreateReg(getMemSegReg())); in addSrcIdxOperands()
434 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg())); in addDstIdxOperands()
444 Inst.addOperand(MCOperand::CreateReg(getMemSegReg())); in addMemOffsOperands()
456 CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
/external/llvm/lib/Target/ARM/
DARMInstrInfo.cpp41 NopInst.addOperand(MCOperand::CreateReg(0)); in getNoopForMachoTarget()
44 NopInst.addOperand(MCOperand::CreateReg(ARM::R0)); in getNoopForMachoTarget()
45 NopInst.addOperand(MCOperand::CreateReg(ARM::R0)); in getNoopForMachoTarget()
47 NopInst.addOperand(MCOperand::CreateReg(0)); in getNoopForMachoTarget()
48 NopInst.addOperand(MCOperand::CreateReg(0)); in getNoopForMachoTarget()
DThumb1InstrInfo.cpp30 NopInst.addOperand(MCOperand::CreateReg(ARM::R8)); in getNoopForMachoTarget()
31 NopInst.addOperand(MCOperand::CreateReg(ARM::R8)); in getNoopForMachoTarget()
33 NopInst.addOperand(MCOperand::CreateReg(0)); in getNoopForMachoTarget()
DARMAsmPrinter.cpp1338 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); in EmitInstruction()
1359 TmpInst.addOperand(MCOperand::CreateReg(0)); in EmitInstruction()
1361 TmpInst.addOperand(MCOperand::CreateReg(0)); in EmitInstruction()
1370 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); in EmitInstruction()
1371 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); in EmitInstruction()
1391 TmpInst.addOperand(MCOperand::CreateReg(0)); in EmitInstruction()
1393 TmpInst.addOperand(MCOperand::CreateReg(0)); in EmitInstruction()
1558 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); in EmitInstruction()
1559 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); in EmitInstruction()
1562 TmpInst.addOperand(MCOperand::CreateReg(0)); in EmitInstruction()
[all …]
/external/llvm/lib/Target/R600/
DSIPrepareScratchRegs.cpp198 MI.addOperand(MachineOperand::CreateReg(Rsrc0, false, true, true)); in runOnMachineFunction()
199 MI.addOperand(MachineOperand::CreateReg(Rsrc1, false, true, true)); in runOnMachineFunction()
200 MI.addOperand(MachineOperand::CreateReg(Rsrc2, false, true, true)); in runOnMachineFunction()
201 MI.addOperand(MachineOperand::CreateReg(Rsrc3, false, true, true)); in runOnMachineFunction()
/external/llvm/lib/Target/AArch64/
DAArch64AsmPrinter.cpp470 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); in EmitInstruction()
503 Adrp.addOperand(MCOperand::CreateReg(AArch64::X0)); in EmitInstruction()
509 Ldr.addOperand(MCOperand::CreateReg(AArch64::X1)); in EmitInstruction()
510 Ldr.addOperand(MCOperand::CreateReg(AArch64::X0)); in EmitInstruction()
517 Add.addOperand(MCOperand::CreateReg(AArch64::X0)); in EmitInstruction()
518 Add.addOperand(MCOperand::CreateReg(AArch64::X0)); in EmitInstruction()
532 Blr.addOperand(MCOperand::CreateReg(AArch64::X1)); in EmitInstruction()
/external/llvm/lib/Target/X86/
DX86InstrBuilder.h65 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, in getFullAddress()
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, in getFullAddress()
81 MO.push_back(MachineOperand::CreateReg(0, false, false, in getFullAddress()
DX86MCInstLower.cpp411 MCOp = MCOperand::CreateReg(MO.getReg()); in Lower()
713 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest in LowerTlsAddr()
714 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base in LowerTlsAddr()
716 LEA.addOperand(MCOperand::CreateReg(0)); // index in LowerTlsAddr()
718 LEA.addOperand(MCOperand::CreateReg(0)); // seg in LowerTlsAddr()
721 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest in LowerTlsAddr()
722 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base in LowerTlsAddr()
724 LEA.addOperand(MCOperand::CreateReg(0)); // index in LowerTlsAddr()
726 LEA.addOperand(MCOperand::CreateReg(0)); // seg in LowerTlsAddr()
729 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest in LowerTlsAddr()
[all …]
/external/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp182 Inst.addOperand(MCOperand::CreateReg(Regs[RegNo])); in decodeRegisterClass()
299 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base])); in decodeMemRIOperands()
306 Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base])); in decodeMemRIOperands()
311 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base])); in decodeMemRIOperands()
327 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base])); in decodeMemRIXOperands()
329 Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base])); in decodeMemRIXOperands()
332 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base])); in decodeMemRIXOperands()
343 Inst.addOperand(MCOperand::CreateReg(CRRegs[7 - Zeros])); in decodeCRBitMOperand()
/external/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp116 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeIntRegsRegisterClass()
127 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeI64RegsRegisterClass()
139 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeFPRegsRegisterClass()
151 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeDFPRegsRegisterClass()
166 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeQFPRegsRegisterClass()
175 Inst.addOperand(MCOperand::CreateReg(FCCRegDecoderTable[RegNo])); in DecodeFCCRegsRegisterClass()
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp264 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeFPR128RegisterClass()
293 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeFPR64RegisterClass()
314 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeFPR32RegisterClass()
335 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeFPR16RegisterClass()
356 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeFPR8RegisterClass()
377 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeGPR64RegisterClass()
389 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeGPR64spRegisterClass()
410 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeGPR32RegisterClass()
423 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeGPR32spRegisterClass()
444 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeVectorRegisterClass()
[all …]
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp585 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
590 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
652 MI.insert(I, MCOperand::CreateReg(0)); in AddThumbPredicate()
654 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); in AddThumbPredicate()
662 MI.insert(I, MCOperand::CreateReg(0)); in AddThumbPredicate()
664 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); in AddThumbPredicate()
897 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeGPRRegisterClass()
921 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); in DecodeGPRwithAPSRRegisterClass()
952 Inst.addOperand(MCOperand::CreateReg(RegisterPair)); in DecodeGPRPairRegisterClass()
982 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodetcGPRRegisterClass()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonExpandPredSpillCode.cpp114 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0, in runOnMachineFunction()
158 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0, in runOnMachineFunction()
198 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0, in runOnMachineFunction()
234 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0, in runOnMachineFunction()
/external/llvm/lib/Target/Mips/
DMipsAsmPrinter.cpp124 TmpInst0.addOperand(MCOperand::CreateReg(ZeroReg)); in emitPseudoIndirectBranch()
784 I.addOperand(MCOperand::CreateReg(Reg)); in EmitInstrReg()
803 I.addOperand(MCOperand::CreateReg(Reg1)); in EmitInstrRegReg()
804 I.addOperand(MCOperand::CreateReg(Reg2)); in EmitInstrRegReg()
813 I.addOperand(MCOperand::CreateReg(Reg1)); in EmitInstrRegRegReg()
814 I.addOperand(MCOperand::CreateReg(Reg2)); in EmitInstrRegRegReg()
815 I.addOperand(MCOperand::CreateReg(Reg3)); in EmitInstrRegRegReg()
/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp253 Inst.addOperand(MCOperand::CreateReg(getReg())); in addRegOperands()
275 Inst.addOperand(MCOperand::CreateReg(getMemBase())); in addMEMrrOperands()
278 Inst.addOperand(MCOperand::CreateReg(getMemOffsetReg())); in addMEMrrOperands()
284 Inst.addOperand(MCOperand::CreateReg(getMemBase())); in addMEMriOperands()
299 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, in CreateReg() function in __anoncba7d3b40111::SparcOperand
610 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); in parseOperand()
662 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E); in parseSparcAsmOperand()
/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp523 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()])); in addRegGPRCOperands()
528 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()])); in addRegGPRCNoR0Operands()
533 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()])); in addRegG8RCOperands()
538 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()])); in addRegG8RCNoX0Operands()
557 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()])); in addRegF4RCOperands()
562 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()])); in addRegF8RCOperands()
567 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()])); in addRegVRRCOperands()
572 Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()])); in addRegVSRCOperands()
577 Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()])); in addRegVSFRCOperands()
582 Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()])); in addRegQFRCOperands()
[all …]
/external/llvm/include/llvm/MC/
DMCInstBuilder.h33 Inst.addOperand(MCOperand::CreateReg(Reg)); in addReg()

123