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Searched refs:DestVT (Results 1 – 17 of 17) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp120 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
121 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
124 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
126 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
127 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
129 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
855 EVT DestVT = TLI.getValueType(I->getType(), true); in selectFPExt() local
857 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in selectFPExt()
878 EVT DestVT = TLI.getValueType(I->getType(), true); in selectFPTrunc() local
880 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in selectFPTrunc()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp159 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
875 EVT DestVT = TLI.getValueType(I->getType(), true); in SelectFPExt() local
877 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in SelectFPExt()
893 EVT DestVT = TLI.getValueType(I->getType(), true); in SelectFPTrunc() local
895 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in SelectFPTrunc()
1138 EVT DestVT = TLI.getValueType(I->getType(), true); in SelectBinaryIntOp() local
1142 if (DestVT != MVT::i16 && DestVT != MVT::i8) in SelectBinaryIntOp()
1310 MVT DestVT = VA.getLocVT(); in processCallArgs() local
1312 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; in processCallArgs()
1314 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false)) in processCallArgs()
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DPPCISelLowering.cpp6495 EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
6496 if (DestVT == MVT::Other) DestVT = Op.getValueType(); in BuildIntrinsicOp()
6497 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
6505 EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
6506 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); in BuildIntrinsicOp()
6507 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
6515 SDLoc dl, EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
6516 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); in BuildIntrinsicOp()
6517 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
/external/llvm/utils/TableGen/
DCallingConvEmitter.cpp224 MVT::SimpleValueType DestVT = getValueType(DestTy); in EmitAction() local
225 O << IndentStr << "LocVT = " << getEnumName(DestVT) <<";\n"; in EmitAction()
226 if (MVT(DestVT).isFloatingPoint()) { in EmitAction()
238 MVT::SimpleValueType DestVT = getValueType(DestTy); in EmitAction() local
239 O << IndentStr << "LocVT = " << getEnumName(DestVT) << ";\n"; in EmitAction()
240 if (MVT(DestVT).isFloatingPoint()) { in EmitAction()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp188 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
189 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
2743 MVT DestVT; in selectFPToInt() local
2744 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector()) in selectFPToInt()
2758 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr; in selectFPToInt()
2760 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr; in selectFPToInt()
2763 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr; in selectFPToInt()
2765 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr; in selectFPToInt()
2768 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass); in selectFPToInt()
2776 MVT DestVT; in selectIntToFP() local
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DAArch64ISelLowering.cpp4612 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); in ReconstructShuffle() local
4619 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
4634 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
4640 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
4645 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
4648 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
4652 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1, in ReconstructShuffle()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp183 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1753 EVT DestVT = TLI.getValueType(I->getType(), true); in SelectBinaryIntOp() local
1757 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) in SelectBinaryIntOp()
1957 MVT DestVT = VA.getLocVT(); in ProcessCallArgs() local
1958 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false); in ProcessCallArgs()
1960 ArgVT = DestVT; in ProcessCallArgs()
1966 MVT DestVT = VA.getLocVT(); in ProcessCallArgs() local
1967 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true); in ProcessCallArgs()
1969 ArgVT = DestVT; in ProcessCallArgs()
2044 MVT DestVT = RVLocs[0].getValVT(); in FinishCall() local
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/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp2926 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType()); in visitICmp() local
2927 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode)); in visitICmp()
2941 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType()); in visitFCmp() local
2942 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition)); in visitFCmp()
2974 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType()); in visitTrunc() local
2975 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N)); in visitTrunc()
2982 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType()); in visitZExt() local
2983 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N)); in visitZExt()
2990 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType()); in visitSExt() local
2991 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N)); in visitSExt()
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DLegalizeDAG.cpp128 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
134 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
136 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
138 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
1777 EVT DestVT, in EmitStackConvert() argument
1791 unsigned DestSize = DestVT.getSizeInBits(); in EmitStackConvert()
1792 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext()); in EmitStackConvert()
1810 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo, in EmitStackConvert()
1814 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, in EmitStackConvert()
2412 EVT DestVT, in ExpandLegalINT_TO_FP() argument
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DLegalizeTypes.cpp907 EVT DestVT) { in CreateStackStoreLoad() argument
911 SDValue StackPtr = DAG.CreateStackTemporary(Op.getValueType(), DestVT); in CreateStackStoreLoad()
916 return DAG.getLoad(DestVT, dl, Store, StackPtr, MachinePointerInfo(), in CreateStackStoreLoad()
DLegalizeVectorTypes.cpp239 EVT DestVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecRes_UnaryOp() local
257 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op); in ScalarizeVecRes_UnaryOp()
1105 EVT DestVT = N->getValueType(0); in SplitVecRes_ExtendOp() local
1107 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT); in SplitVecRes_ExtendOp()
1124 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) { in SplitVecRes_ExtendOp()
DLegalizeTypes.h158 SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp1068 MVT DestVT = TLI->getRegisterType(NewVT); in getVectorTypeBreakdownMVT() local
1069 RegisterVT = DestVT; in getVectorTypeBreakdownMVT()
1070 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdownMVT()
1071 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); in getVectorTypeBreakdownMVT()
1437 MVT DestVT = getRegisterType(Context, NewVT); in getVectorTypeBreakdown() local
1438 RegisterVT = DestVT; in getVectorTypeBreakdown()
1445 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdown()
1446 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); in getVectorTypeBreakdown()
/external/llvm/lib/Target/R600/
DAMDGPUISelDAGToDAG.cpp1115 EVT DestVT = ASC->getValueType(0); in SelectAddrSpaceCast() local
1119 unsigned DestSize = DestVT.getSizeInBits(); in SelectAddrSpaceCast()
1126 DestVT, in SelectAddrSpaceCast()
1153 return CurDAG->getNode(ISD::BITCAST, DL, DestVT, Src).getNode(); in SelectAddrSpaceCast()
DAMDGPUISelLowering.cpp543 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const { in isNarrowingProfitable()
550 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32; in isNarrowingProfitable()
2170 EVT DestVT = Op.getValueType(); in LowerUINT_TO_FP() local
2171 if (DestVT == MVT::f64) in LowerUINT_TO_FP()
2174 assert(DestVT == MVT::f32); in LowerUINT_TO_FP()
/external/llvm/include/llvm/Target/
DTargetLowering.h1353 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in AddPromotedToType() argument
1354 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; in AddPromotedToType()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp11593 EVT DestVT = Op.getValueType(); in LowerUINT_TO_FP_i32() local
11595 if (DestVT.bitsLT(MVT::f64)) in LowerUINT_TO_FP_i32()
11596 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, in LowerUINT_TO_FP_i32()
11598 if (DestVT.bitsGT(MVT::f64)) in LowerUINT_TO_FP_i32()
11599 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); in LowerUINT_TO_FP_i32()