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Searched refs:OpIdx (Results 1 – 25 of 38) sorted by relevance

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/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp61 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
67 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
73 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
79 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
85 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
92 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
98 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
104 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
110 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
115 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp81 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
85 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
92 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
98 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
103 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
108 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
113 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
125 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
131 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
/external/llvm/utils/TableGen/
DCodeEmitterGen.cpp87 unsigned OpIdx; in AddCodeToMergeInOperand() local
88 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { in AddCodeToMergeInOperand()
90 OpIdx = CGI.Operands[OpIdx].MIOperandNo; in AddCodeToMergeInOperand()
91 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && in AddCodeToMergeInOperand()
114 OpIdx = NumberedOp++; in AddCodeToMergeInOperand()
117 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx); in AddCodeToMergeInOperand()
128 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); in AddCodeToMergeInOperand()
134 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")"; in AddCodeToMergeInOperand()
193 unsigned OpIdx; in getInstructionCase() local
194 if (!CGI.Operands.hasOperandNamed(Vals[i].getName(), OpIdx)) in getInstructionCase()
[all …]
DCodeGenInstruction.cpp137 unsigned OpIdx; in getOperandNamed() local
138 if (hasOperandNamed(Name, OpIdx)) return OpIdx; in getOperandNamed()
146 bool CGIOperandList::hasOperandNamed(StringRef Name, unsigned &OpIdx) const { in hasOperandNamed()
150 OpIdx = i; in hasOperandNamed()
173 unsigned OpIdx = getOperandNamed(OpName); in ParseOperandName() local
177 if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp && in ParseOperandName()
183 return std::make_pair(OpIdx, 0U); in ParseOperandName()
187 DagInit *MIOpInfo = OperandList[OpIdx].MIOperandInfo; in ParseOperandName()
194 return std::make_pair(OpIdx, i); in ParseOperandName()
DFixedLenDecoderEmitter.cpp1728 unsigned OpIdx; in populateInstruction() local
1729 if (!CGI.Operands.hasOperandNamed(Vals[i].getName(), OpIdx)) in populateInstruction()
1732 NamedOpIndices.insert(OpIdx); in populateInstruction()
1759 unsigned OpIdx; in populateInstruction() local
1760 if (CGI.Operands.hasOperandNamed(Vals[i].getName(), OpIdx)) in populateInstruction()
1789 OpIdx = NumberedOp++; in populateInstruction()
1793 CGI.Operands.getSubOperandNumber(OpIdx); in populateInstruction()
/external/llvm/lib/Target/AArch64/
DAArch64AddressTypePromotion.cpp207 static bool shouldSExtOperand(const Instruction *Inst, int OpIdx) { in shouldSExtOperand() argument
208 if (isa<SelectInst>(Inst) && OpIdx == 0) in shouldSExtOperand()
312 for (int OpIdx = 0, EndOpIdx = Inst->getNumOperands(); OpIdx != EndOpIdx; in propagateSignExtension() local
313 ++OpIdx) { in propagateSignExtension()
314 DEBUG(dbgs() << "Operand:\n" << *(Inst->getOperand(OpIdx)) << '\n'); in propagateSignExtension()
315 if (Inst->getOperand(OpIdx)->getType() == SExt->getType() || in propagateSignExtension()
316 !shouldSExtOperand(Inst, OpIdx)) { in propagateSignExtension()
321 Value *Opnd = Inst->getOperand(OpIdx); in propagateSignExtension()
324 Inst->setOperand(OpIdx, ConstantInt::getSigned(SExt->getType(), in propagateSignExtension()
331 Inst->setOperand(OpIdx, UndefValue::get(SExt->getType())); in propagateSignExtension()
[all …]
DAArch64PromoteConstant.cpp240 unsigned OpIdx) { in shouldConvertUse() argument
243 if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2) in shouldConvertUse()
247 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0) in shouldConvertUse()
251 if (isa<const InsertValueInst>(Instr) && OpIdx > 1) in shouldConvertUse()
254 if (isa<const AllocaInst>(Instr) && OpIdx > 0) in shouldConvertUse()
258 if (isa<const LoadInst>(Instr) && OpIdx > 0) in shouldConvertUse()
262 if (isa<const StoreInst>(Instr) && OpIdx > 1) in shouldConvertUse()
266 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0) in shouldConvertUse()
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp391 unsigned OpIdx = 0; in ExpandVLD() local
393 bool DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandVLD()
394 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandVLD()
406 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
409 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
410 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
413 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
420 SrcOpIdx = OpIdx++; in ExpandVLD()
423 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
424 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
[all …]
/external/llvm/lib/CodeGen/
DMachineInstr.cpp996 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, in findInlineAsmFlagIdx() argument
999 assert(OpIdx < getNumOperands() && "OpIdx out of range"); in findInlineAsmFlagIdx()
1002 if (OpIdx < InlineAsm::MIOp_FirstOperand) in findInlineAsmFlagIdx()
1014 if (i + NumOps > OpIdx) { in findInlineAsmFlagIdx()
1025 MachineInstr::getRegClassConstraint(unsigned OpIdx, in getRegClassConstraint() argument
1034 return TII->getRegClass(getDesc(), OpIdx, TRI, MF); in getRegClassConstraint()
1036 if (!getOperand(OpIdx).isReg()) in getRegClassConstraint()
1041 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
1042 OpIdx = DefIdx; in getRegClassConstraint()
1045 int FlagIdx = findInlineAsmFlagIdx(OpIdx); in getRegClassConstraint()
[all …]
DExecutionDepsFix.cpp201 bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref);
474 bool ExeDepsFix::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, in shouldBreakDependence() argument
476 unsigned reg = MI->getOperand(OpIdx).getReg(); in shouldBreakDependence()
560 unsigned OpIdx = UndefReads.back().second; in processUndefReads() local
568 if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg())) in processUndefReads()
569 TII->breakPartialRegDependency(UndefMI, OpIdx, TRI); in processUndefReads()
576 OpIdx = UndefReads.back().second; in processUndefReads()
DTargetInstrInfo.cpp888 for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx; in getRegSequenceInputs() local
889 OpIdx += 2) { in getRegSequenceInputs()
890 const MachineOperand &MOReg = MI.getOperand(OpIdx); in getRegSequenceInputs()
891 const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1); in getRegSequenceInputs()
DPeepholeOptimizer.cpp1228 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; in getNextSourceFromBitcast() local
1229 ++OpIdx) { in getNextSourceFromBitcast()
1230 const MachineOperand &MO = Def->getOperand(OpIdx); in getNextSourceFromBitcast()
1237 SrcIdx = OpIdx; in getNextSourceFromBitcast()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h934 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
944 getRegClassConstraint(unsigned OpIdx,
975 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
990 unsigned findTiedOperandIdx(unsigned OpIdx) const;
1181 void untieRegOperand(unsigned OpIdx) {
1182 MachineOperand &MO = getOperand(OpIdx);
1184 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1211 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
DScheduleDAGInstrs.h49 int OpIdx; member
52 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {} in PhysRegSUOper()
/external/llvm/lib/MC/MCDisassembler/
DDisassembler.cpp172 for (unsigned OpIdx = 0, OpIdxEnd = Inst.getNumOperands(); OpIdx != OpIdxEnd; in getItineraryLatency() local
173 ++OpIdx) in getItineraryLatency()
174 Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx)); in getItineraryLatency()
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
DR600MCCodeEmitter.cpp63 void EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const;
234 void R600MCCodeEmitter::EmitSrc(const MCInst &MI, unsigned OpIdx, in EmitSrc() argument
236 const MCOperand &MO = MI.getOperand(OpIdx); in EmitSrc()
271 if ((!(isFlagSet(MI, OpIdx, MO_FLAG_ABS))) in EmitSrc()
272 && (isFlagSet(MI, OpIdx, MO_FLAG_NEG) || in EmitSrc()
281 if (isFlagSet(MI, OpIdx, MO_FLAG_ABS)) { in EmitSrc()
/external/llvm/lib/Target/R600/
DR600ExpandSpecialInstrs.cpp61 int OpIdx = TII->getOperandIdx(*OldMI, Op); in SetFlagInNewMI() local
62 if (OpIdx > -1) { in SetFlagInNewMI()
63 uint64_t Val = OldMI->getOperand(OpIdx).getImm(); in SetFlagInNewMI()
DSIInstrInfo.h285 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
289 bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
DSIInstrInfo.cpp1337 for (int OpIdx : OpIndices) { in verifyInstruction() local
1338 if (OpIdx == -1) in verifyInstruction()
1340 const MachineOperand &MO = MI->getOperand(OpIdx); in verifyInstruction()
1341 if (usesConstantBus(MRI, MO, getOpSize(Opcode, OpIdx))) { in verifyInstruction()
1465 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const { in legalizeOpWithMove()
1468 MachineOperand &MO = MI->getOperand(OpIdx); in legalizeOpWithMove()
1470 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass; in legalizeOpWithMove()
1580 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx, in isOperandLegal() argument
1584 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx]; in isOperandLegal()
1588 MO = &MI->getOperand(OpIdx); in isOperandLegal()
[all …]
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.h40 virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
170 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
/external/llvm/lib/Target/Sparc/InstPrinter/
DSparcInstPrinter.h42 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
/external/llvm/lib/Target/Mips/InstPrinter/
DMipsInstPrinter.h93 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
/external/llvm/lib/ExecutionEngine/RuntimeDyld/
DRuntimeDyldChecker.cpp254 unsigned OpIdx = OpIdxExpr.getValue(); in evalDecodeOperand() local
255 if (OpIdx >= Inst.getNumOperands()) { in evalDecodeOperand()
258 ErrMsgStream << "Invalid operand index '" << format("%i", OpIdx) in evalDecodeOperand()
267 const MCOperand &Op = Inst.getOperand(OpIdx); in evalDecodeOperand()
271 ErrMsgStream << "Operand '" << format("%i", OpIdx) << "' of instruction '" in evalDecodeOperand()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.h103 unsigned OpIdx, SDep& dep) const;
DScheduleDAGSDNodes.cpp628 unsigned OpIdx, SDep& dep) const{ in computeOperandLatency() argument
636 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency()
639 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs(); in computeOperandLatency()
640 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency()

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