Home
last modified time | relevance | path

Searched refs:OpNode (Results 1 – 25 of 30) sorted by relevance

12

/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td1230 SDNode OpNode>
1232 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1235 SDNode OpNode>
1237 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1243 SDNode OpNode, SDNode OpNode_setflags> {
1244 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1248 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1267 SDPatternOperator OpNode>
1270 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> {
1283 SDPatternOperator OpNode>
[all …]
/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.h81 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
83 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
85 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
88 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
90 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
92 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
DNVPTXInstrInfo.td165 multiclass I3<string OpcStr, SDNode OpNode> {
168 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
172 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
175 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
179 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
182 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
186 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, (imm):$b))]>;
189 multiclass ADD_SUB_INT_32<string OpcStr, SDNode OpNode> {
193 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
197 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
[all …]
DNVPTXVector.td241 class VecBinaryOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass,
245 [(set regclass:$dst, (OpNode regclass:$a, regclass:$b))],
248 class VecShiftOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass1,
252 [(set regclass1:$dst, (OpNode regclass1:$a, regclass2:$b))],
255 class VecUnaryOp<BinOpAsmString asmstr, PatFrag OpNode, NVPTXRegClass regclass,
259 [(set regclass:$dst, (OpNode regclass:$a))], sInst>;
261 multiclass IntBinVOp<string asmstr, SDNode OpNode,
264 def V2I64 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "64")>, OpNode, V2I64Regs,
266 def V4I32 : VecBinaryOp<V4AsmStr<!strconcat(asmstr, "32")>, OpNode, V4I32Regs,
268 def V2I32 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "32")>, OpNode, V2I32Regs,
[all …]
DNVPTXISelDAGToDAG.cpp4959 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) { in SelectADDRsi_imp() argument
4973 bool NVPTXDAGToDAGISel::SelectADDRsi(SDNode *OpNode, SDValue Addr, in SelectADDRsi() argument
4975 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i32); in SelectADDRsi()
4979 bool NVPTXDAGToDAGISel::SelectADDRsi64(SDNode *OpNode, SDValue Addr, in SelectADDRsi64() argument
4981 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i64); in SelectADDRsi64()
4986 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) { in SelectADDRri_imp() argument
5015 bool NVPTXDAGToDAGISel::SelectADDRri(SDNode *OpNode, SDValue Addr, in SelectADDRri() argument
5017 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i32); in SelectADDRri()
5021 bool NVPTXDAGToDAGISel::SelectADDRri64(SDNode *OpNode, SDValue Addr, in SelectADDRri64() argument
5023 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i64); in SelectADDRri64()
/external/llvm/lib/Target/X86/
DX86InstrAVX512.td632 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
636 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
643 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
648 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
650 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
654 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
679 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
682 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
688 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
693 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
[all …]
DX86InstrFMA.td133 SDPatternOperator OpNode = null_frag> {
140 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
148 (OpVT (OpNode RC:$src2, RC:$src1,
155 SDNode OpNode, RegisterClass RC, ValueType OpVT,
175 OpNode>;
180 SDNode OpNode> {
181 defm SS : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", "SS", IntF32, OpNode,
183 defm SD : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", "PD", IntF64, OpNode,
220 X86MemOperand x86memop, ValueType OpVT, SDNode OpNode,
228 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG, MemOp4;
[all …]
DX86InstrFPStack.td127 multiclass FPBinary_rr<SDNode OpNode> {
131 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
133 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
135 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
140 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
145 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
149 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
153 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>;
157 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>;
161 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>;
[all …]
DX86InstrSSE.td242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
251 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
258 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
289 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
298 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
305 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
549 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
555 [(set VR128:$dst, (vt (OpNode VR128:$src1,
567 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
571 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
[all …]
DX86InstrCMovSetCC.td83 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
87 [(set GR8:$dst, (X86setcc OpNode, EFLAGS))],
91 [(store (X86setcc OpNode, EFLAGS), addr:$dst)],
/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td258 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
264 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
268 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
274 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
278 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
284 list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
288 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
294 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
298 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
304 list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
[all …]
DMipsInstrFPU.td103 SDPatternOperator OpNode= null_frag> :
106 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr> {
111 SDPatternOperator OpNode = null_frag> {
112 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
115 IsComm, OpNode>,
122 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
128 SDPatternOperator OpNode= null_frag> {
129 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
131 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
[all …]
DMipsMSAInstrInfo.td1143 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1150 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1154 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1161 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1165 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1172 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1176 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1183 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1188 class MSA_BIT_B_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1194 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt3:$m))];
[all …]
DMipsInstrInfo.td588 SDPatternOperator OpNode = null_frag>:
591 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
601 SDPatternOperator OpNode = null_frag> :
604 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
630 SDPatternOperator OpNode = null_frag,
634 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
639 SDPatternOperator OpNode = null_frag>:
642 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
654 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
657 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
[all …]
DMicroMipsInstrInfo.td177 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
181 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
187 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
191 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
262 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
266 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
274 SDPatternOperator OpNode = null_frag> :
277 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
288 SDPatternOperator OpNode = null_frag> :
291 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
[all …]
DMipsCondMov.td36 SDPatternOperator OpNode = null_frag> :
39 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
46 SDPatternOperator OpNode = null_frag> :
49 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
DMips16InstrInfo.td1305 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1306 Mips16Pat<(OpNode CPU16Regs:$r),
1312 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1313 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1325 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1326 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1335 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1336 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1343 class LoadM16_pat<PatFrag OpNode, Instruction I> :
1344 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
[all …]
/external/llvm/lib/Target/BPF/
DBPFInstrInfo.td139 class ALU_RI<bits<4> Opc, string OpcodeStr, SDNode OpNode>
142 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]> {
158 class ALU_RR<bits<4> Opc, string OpcodeStr, SDNode OpNode>
161 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]> {
177 multiclass ALU<bits<4> Opc, string OpcodeStr, SDNode OpNode> {
178 def _rr : ALU_RR<Opc, OpcodeStr, OpNode>;
179 def _ri : ALU_RI<Opc, OpcodeStr, OpNode>;
306 class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag OpNode>
307 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
334 class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td2435 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2438 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2441 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2444 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2500 ValueType TyD, ValueType TyQ, SDNode OpNode>
2503 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2518 ValueType TyQ, ValueType TyD, SDNode OpNode>
2521 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2547 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2551 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
[all …]
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.td220 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
223 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
226 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
237 SDNode OpNode> {
240 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
243 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
246 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
249 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
258 SDNode OpNode> {
261 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstrFormats.td209 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
213 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>;
216 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>;
DSparcInstrInfo.td249 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
254 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>;
258 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
273 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
278 [(set Ty:$dst, (OpNode ADDRrr:$addr))]>;
282 [(set Ty:$dst, (OpNode ADDRri:$addr))]>;
286 multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
291 [(OpNode Ty:$rd, ADDRrr:$addr)]>;
295 [(OpNode Ty:$rd, ADDRri:$addr)]>;
/external/llvm/utils/TableGen/
DCodeGenDAGPatterns.cpp3017 TreePatternNode *OpNode = InVal->clone(); in parseInstructionPattern() local
3020 OpNode->clearPredicateFns(); in parseInstructionPattern()
3023 if (Record *Xform = OpNode->getTransformFn()) { in parseInstructionPattern()
3024 OpNode->setTransformFn(nullptr); in parseInstructionPattern()
3026 Children.push_back(OpNode); in parseInstructionPattern()
3027 OpNode = new TreePatternNode(Xform, Children, OpNode->getNumTypes()); in parseInstructionPattern()
3030 ResultNodeOperands.push_back(OpNode); in parseInstructionPattern()
3481 TreePatternNode *OpNode = DstPattern->getChild(ii); in ParsePatterns() local
3482 if (Record *Xform = OpNode->getTransformFn()) { in ParsePatterns()
3483 OpNode->setTransformFn(nullptr); in ParsePatterns()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DSIISelLowering.cpp299 SDValue OpNode = DAG.getNode(VCCNode, DL, MVT::i64, in Loweri1ContextSwitch() local
305 return DAG.getNode(SIISD::VCC_BITCAST, DL, MVT::i1, OpNode); in Loweri1ContextSwitch()
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td96 class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred>
97 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
404 multiclass Addri_base<string mnemonic, SDNode OpNode> {
428 class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp>
432 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10))]> {
4454 class S_2OpInstImmI6<string Mnemonic, SDNode OpNode, bits<3>MinOp>
4456 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
5275 multiclass xtype_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
5277 defm _acc : xtype_imm_base< opc1, "+= ", OpNode, add, 0b001, minOp>;
5279 defm _nac : xtype_imm_base< opc1, "-= ", OpNode, sub, 0b000, minOp>;
[all …]

12