| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 410 unsigned ResultReg = in selectBinaryOp() local
413 if (!ResultReg) in selectBinaryOp()
417 updateValueMap(I, ResultReg); in selectBinaryOp()
444 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, in selectBinaryOp() local
446 if (!ResultReg) in selectBinaryOp()
450 updateValueMap(I, ResultReg); in selectBinaryOp()
456 unsigned ResultReg = fastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), in selectBinaryOp() local
458 if (ResultReg) { in selectBinaryOp()
460 updateValueMap(I, ResultReg); in selectBinaryOp()
471 unsigned ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), in selectBinaryOp() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 323 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); in fastMaterializeAlloca() local
325 ResultReg) in fastMaterializeAlloca()
329 return ResultReg; in fastMaterializeAlloca()
346 unsigned ResultReg = createResultReg(RC); in materializeInt() local
348 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
349 return ResultReg; in materializeInt()
383 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
385 TII.get(TargetOpcode::COPY), ResultReg) in materializeFP()
388 return ResultReg; in materializeFP()
403 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
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| D | AArch64InstrInfo.cpp | 2598 unsigned ResultReg = Root.getOperand(0).getReg(); in genMadd() local
2606 if (TargetRegisterInfo::isVirtualRegister(ResultReg)) in genMadd()
2607 MRI.constrainRegClass(ResultReg, RC); in genMadd()
2616 ResultReg) in genMadd()
2648 unsigned ResultReg = Root.getOperand(0).getReg(); in genMaddR() local
2654 if (TargetRegisterInfo::isVirtualRegister(ResultReg)) in genMaddR()
2655 MRI.constrainRegClass(ResultReg, RC); in genMaddR()
2664 ResultReg) in genMaddR()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 87 unsigned &ResultReg, unsigned Alignment = 1);
96 unsigned &ResultReg);
330 MachineMemOperand *MMO, unsigned &ResultReg, in X86FastEmitLoad() argument
402 ResultReg = createResultReg(RC); in X86FastEmitLoad()
404 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg); in X86FastEmitLoad()
524 unsigned &ResultReg) { in X86FastEmitExtend() argument
530 ResultReg = RR; in X86FastEmitExtend()
1101 unsigned ResultReg = 0; in X86SelectLoad() local
1102 if (!X86FastEmitLoad(VT, AM, createMachineMemOperandFor(LI), ResultReg, in X86SelectLoad()
1106 updateValueMap(I, ResultReg); in X86SelectLoad()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 114 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
235 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp() local
236 if (!ResultReg) in emitLogicalOp()
251 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
252 return ResultReg; in emitLogicalOp()
270 unsigned ResultReg = createResultReg(RC); in materialize32BitInt() local
274 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
275 return ResultReg; in materialize32BitInt()
277 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
278 return ResultReg; in materialize32BitInt()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 173 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
289 unsigned ResultReg = createResultReg(RC); in fastEmitInst_r() local
297 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
302 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_r()
305 return ResultReg; in fastEmitInst_r()
312 unsigned ResultReg = createResultReg(RC); in fastEmitInst_rr() local
322 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_rr()
330 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_rr()
333 return ResultReg; in fastEmitInst_rr()
341 unsigned ResultReg = createResultReg(RC); in fastEmitInst_rrr() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 152 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
412 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); in PPCSimplifyAddress() local
414 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0); in PPCSimplifyAddress()
415 Addr.Base.Reg = ResultReg; in PPCSimplifyAddress()
432 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, in PPCEmitLoad() argument
446 (ResultReg ? MRI.getRegClass(ResultReg) : in PPCEmitLoad()
494 bool IsVSFRC = (ResultReg != 0) && isVSFRCRegister(ResultReg); in PPCEmitLoad()
501 if (ResultReg == 0) in PPCEmitLoad()
502 ResultReg = createResultReg(UseRC); in PPCEmitLoad()
517 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in PPCEmitLoad()
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| /external/llvm/include/llvm/CodeGen/ |
| D | FastISel.h | 76 unsigned ResultReg; member
92 ResultReg(0), NumResultRegs(0), IsPatchPoint(false) {} in CallLoweringInfo()
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| /external/llvm/lib/Target/R600/ |
| D | SIInstrInfo.cpp | 2457 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitBCNT() local
2470 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg) in splitScalar64BitBCNT()
2474 MRI.replaceRegWith(Dest.getReg(), ResultReg); in splitScalar64BitBCNT()
2503 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); in splitScalar64BitBFE() local
2514 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg) in splitScalar64BitBFE()
2520 MRI.replaceRegWith(Dest.getReg(), ResultReg); in splitScalar64BitBFE()
2526 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); in splitScalar64BitBFE() local
2532 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg) in splitScalar64BitBFE()
2538 MRI.replaceRegWith(Dest.getReg(), ResultReg); in splitScalar64BitBFE()
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