Home
last modified time | relevance | path

Searched refs:addv (Results 1 – 25 of 27) sorted by relevance

12

/external/llvm/test/CodeGen/Mips/msa/
Dspill.ll76 %r1 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %1)
77 %r2 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r1, <16 x i8> %2)
78 %r3 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r2, <16 x i8> %3)
79 %r4 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r3, <16 x i8> %4)
80 %r5 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r4, <16 x i8> %5)
81 %r6 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r5, <16 x i8> %6)
82 %r7 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r6, <16 x i8> %7)
83 %r8 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r7, <16 x i8> %8)
84 %r9 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r8, <16 x i8> %9)
85 %r10 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r9, <16 x i8> %10)
[all …]
Dbitcast.ll9 %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)
11 %3 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %2, <16 x i8> %2)
18 ; LITENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
19 ; LITENDIAN: addv.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]
25 ; BIGENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
26 ; BIGENDIAN: addv.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]
33 %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)
35 %3 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %2, <8 x i16> %2)
42 ; LITENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
43 ; LITENDIAN: addv.h [[R3:\$w[0-9]+]], [[R2]], [[R2]]
[all …]
Dbasic_operations.ll265 ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
284 ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
303 ; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
319 ; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
338 ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
356 ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
374 ; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
390 ; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
409 ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
433 ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
[all …]
D3r-a.ll420 %2 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %1)
425 declare <16 x i8> @llvm.mips.addv.b(<16 x i8>, <16 x i8>) nounwind
432 ; CHECK-DAG: addv.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]
445 %2 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %1)
450 declare <8 x i16> @llvm.mips.addv.h(<8 x i16>, <8 x i16>) nounwind
457 ; CHECK-DAG: addv.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]
470 %2 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %1)
475 declare <4 x i32> @llvm.mips.addv.w(<4 x i32>, <4 x i32>) nounwind
482 ; CHECK-DAG: addv.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]
495 %2 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %1)
[all …]
Darithmetic.ll12 ; CHECK-DAG: addv.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
28 ; CHECK-DAG: addv.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
44 ; CHECK-DAG: addv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
60 ; CHECK-DAG: addv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
/external/llvm/test/MC/AArch64/
Dneon-across.s81 addv b0, v1.8b
82 addv b0, v1.16b
83 addv h0, v1.4h
84 addv h0, v1.8h
85 addv s0, v1.4s
Ddot-req.s28 addv bob, v0.8b
Darm64-advsimd.s73 addv.8b b0, v0
74 addv.16b b0, v0
75 addv.4h h0, v0
76 addv.8h h0, v0
77 addv.4s s0, v0
79 ; CHECK: addv.8b b0, v0 ; encoding: [0x00,0xb8,0x31,0x0e]
80 ; CHECK: addv.16b b0, v0 ; encoding: [0x00,0xb8,0x31,0x4e]
81 ; CHECK: addv.4h h0, v0 ; encoding: [0x00,0xb8,0x71,0x0e]
82 ; CHECK: addv.8h h0, v0 ; encoding: [0x00,0xb8,0x71,0x4e]
83 ; CHECK: addv.4s s0, v0 ; encoding: [0x00,0xb8,0xb1,0x4e]
Dneon-diagnostics.s3777 addv s0, v1.2s
3799 addv d0, v1.2d define
/external/llvm/test/CodeGen/AArch64/
Darm64-vaddv.ll5 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
16 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1
28 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
39 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1
94 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
105 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1
117 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
128 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
139 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1
151 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
[all …]
Darm64-neon-across.ll343 ; CHECK: addv b{{[0-9]+}}, {{v[0-9]+}}.8b
352 ; CHECK: addv h{{[0-9]+}}, {{v[0-9]+}}.4h
361 ; CHECK: addv b{{[0-9]+}}, {{v[0-9]+}}.8b
370 ; CHECK: addv h{{[0-9]+}}, {{v[0-9]+}}.4h
379 ; CHECK: addv b{{[0-9]+}}, {{v[0-9]+}}.16b
388 ; CHECK: addv h{{[0-9]+}}, {{v[0-9]+}}.8h
397 ; CHECK: addv s{{[0-9]+}}, {{v[0-9]+}}.4s
405 ; CHECK: addv b{{[0-9]+}}, {{v[0-9]+}}.16b
414 ; CHECK: addv h{{[0-9]+}}, {{v[0-9]+}}.8h
423 ; CHECK: addv s{{[0-9]+}}, {{v[0-9]+}}.4s
/external/llvm/test/CodeGen/SystemZ/
Dint-add-16.ll17 %addv = bitcast i128 %add to <2 x i64>
18 %high = extractelement <2 x i64> %addv, i32 0
20 %low = extractelement <2 x i64> %addv, i32 1
/external/llvm/test/MC/Mips/msa/
Dtest_3r.s19 # CHECK: addv.b $w24, $w20, $w21 # encoding: [0x78,0x15,0xa6,0x0e]
20 # CHECK: addv.h $w4, $w13, $w27 # encoding: [0x78,0x3b,0x69,0x0e]
21 # CHECK: addv.w $w19, $w11, $w14 # encoding: [0x78,0x4e,0x5c,0xce]
22 # CHECK: addv.d $w2, $w21, $w31 # encoding: [0x78,0x7f,0xa8,0x8e]
262 addv.b $w24, $w20, $w21
263 addv.h $w4, $w13, $w27
264 addv.w $w19, $w11, $w14
265 addv.d $w2, $w21, $w31
/external/llvm/test/MC/Disassembler/Mips/msa/
Dtest_3r.txt19 0x78 0x15 0xa6 0x0e # CHECK: addv.b $w24, $w20, $w21
20 0x78 0x3b 0x69 0x0e # CHECK: addv.h $w4, $w13, $w27
21 0x78 0x4e 0x5c 0xce # CHECK: addv.w $w19, $w11, $w14
22 0x78 0x7f 0xa8 0x8e # CHECK: addv.d $w2, $w21, $w31
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt77 # CHECK: addv.8b b0, v0
78 # CHECK: addv.16b b0, v0
79 # CHECK: addv.4h h0, v0
80 # CHECK: addv.8h h0, v0
81 # CHECK: addv.4s s0, v0
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td1588 class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable;
1589 class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable;
1590 class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable;
1591 class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable;
/external/vixl/src/vixl/a64/
Dsimulator-a64.h1868 LogicVRegister addv(VectorFormat vform,
Dmacro-assembler-a64.h2225 V(addv, Addv) \
Dassembler-a64.h2926 void addv(const VRegister& vd,
Dsimulator-a64.cc2835 case NEON_ADDV: addv(vf, rd, rn); break; in VisitNEONAcrossLanes()
Dlogic-a64.cc1398 LogicVRegister Simulator::addv(VectorFormat vform, in addv() function in vixl::Simulator
Dassembler-a64.cc4032 V(addv, NEON_ADDV, true) \
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp26979 addv s22, v23.4s 6b19413249a545868f92f83002763d69 1c1d2688112d4dfab082d41c30cdc76b 000000000000…
26980 addv h22, v23.8h beb8024dd96c5f84afead12f81eba359 64395186879cdf1381e84be7826c8ad1 000000000000…
26981 addv h22, v23.4h c53cafcaa6895f85f6ebe9b3713c0332 f631411f52dbb0e811eedb705e5ea0d6 000000000000…
26982 addv b22, v23.16b e085a98910dea66ac575a29e3247bed2 35e65431d3c81f59c175e3972383685c 00000000000…
26983 addv b22, v23.8b 7e38ed9d69448d46f05ec33b31bb4341 1e5d71ec499d7577ebffe6a62ff141a4 000000000000…
/external/vixl/test/
Dtest-simulator-a64.cc4032 DEFINE_TEST_NEON_ACROSS(addv, Basic)
/external/vixl/doc/
Dsupported-instructions.md1458 void addv(const VRegister& vd,

12