| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 87 v8i64 = 40, // 8 x i64 enumerator
242 SimpleTy == MVT::v8i64 || SimpleTy == MVT::v16i32); in is512BitVector()
311 case v8i64: in getVectorElementType()
347 case v8i64: in getVectorNumElements()
442 case v8i64: in getSizeInBits()
562 if (NumElements == 8) return MVT::v8i64; in getVectorVT()
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| D | ValueTypes.td | 63 def v8i64 : ValueType<512, 40>; // 8 x i64 vector value
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| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 131 { ISD::SHL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
132 { ISD::SRL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
133 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
504 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, in getCastInstrCost()
505 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, in getCastInstrCost()
506 { ISD::TRUNCATE, MVT::v16i32, MVT::v8i64, 4 }, in getCastInstrCost()
516 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v16i32, 3 }, in getCastInstrCost()
517 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v16i32, 3 }, in getCastInstrCost()
565 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, in getCastInstrCost()
598 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 }, in getCastInstrCost()
[all …]
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| D | X86CallingConv.td | 57 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
111 CCIfType<[v16f32, v8f64, v16i32, v8i64],
138 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
277 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
297 CCIfType<[v16i32, v8i64, v16f32, v8f64],
320 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
363 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
465 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
476 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
523 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
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| D | X86InstrAVX512.td | 83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
293 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
298 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
303 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
304 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
305 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
306 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
307 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
308 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
313 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
[all …]
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| D | X86InstrFragmentsSIMD.td | 377 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
462 (v8i64 (alignedload512 node:$ptr))>;
546 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
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| D | X86ISelLowering.cpp | 1245 addRegisterClass(MVT::v8i64, &X86::VR512RegClass); in X86TargetLowering()
1262 setOperationAction(ISD::LOAD, MVT::v8i64, Legal); in X86TargetLowering()
1314 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom); in X86TargetLowering()
1316 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom); in X86TargetLowering()
1333 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom); in X86TargetLowering()
1341 setOperationAction(ISD::MUL, MVT::v8i64, Custom); in X86TargetLowering()
1350 setOperationAction(ISD::SELECT, MVT::v8i64, Custom); in X86TargetLowering()
1353 setOperationAction(ISD::ADD, MVT::v8i64, Legal); in X86TargetLowering()
1356 setOperationAction(ISD::SUB, MVT::v8i64, Legal); in X86TargetLowering()
1361 setOperationAction(ISD::SRL, MVT::v8i64, Custom); in X86TargetLowering()
[all …]
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| D | X86RegisterInfo.td | 457 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64], 512,
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| D | X86InstrCompiler.td | 518 defm _V8I64 : CMOVrr_PSEUDO<VR512, v8i64>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 93 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
94 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
95 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
96 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
281 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 }, in getCmpSelInstrCost()
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| D | ARMRegisterInfo.td | 387 def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (add Tuples2QQ)> {
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| D | ARMISelDAGToDAG.cpp | 2021 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVST()
2142 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
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| D | ARMISelLowering.cpp | 999 case MVT::v8i64: in findRepresentativeClass()
1155 if (VT == MVT::v8i64) in getRegClassFor()
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 158 case MVT::v8i64: return "v8i64"; in getEVTString()
226 case MVT::v8i64: return VectorType::get(Type::getInt64Ty(Context), 8); in getTypeForEVT()
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| /external/llvm/test/CodeGen/R600/ |
| D | ctpop64.ll | 7 declare <8 x i64> @llvm.ctpop.v8i64(<8 x i64>) nounwind readnone
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64TargetTransformInfo.cpp | 363 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost }, in getCmpSelInstrCost()
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86InstComments.cpp | 528 DecodeUNPCKHMask(MVT::v8i64, ShuffleMask); in EmitAnyX86InstComments()
617 DecodeUNPCKLMask(MVT::v8i64, ShuffleMask); in EmitAnyX86InstComments()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 100 case MVT::v8i64: return "MVT::v8i64"; in getEnumName()
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 181 def llvm_v8i64_ty : LLVMType<v8i64>; // 8 x i64
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| /external/llvm/test/CodeGen/X86/ |
| D | avx512-intrinsics.ll | 336 %res = call <8 x i64> @llvm.ctlz.v8i64(<8 x i64> %a, i1 false)
340 declare <8 x i64> @llvm.ctlz.v8i64(<8 x i64>, i1) nounwind readonly
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