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Searched refs:SRL (Results 1 – 25 of 85) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp129 { ISD::SRL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
132 { ISD::SRL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
140 { ISD::SRL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
143 { ISD::SRL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
146 { ISD::SRL, MVT::v2i64, 1 }, in getArithmeticInstrCost()
148 { ISD::SRL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
153 { ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized. in getArithmeticInstrCost()
154 { ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized. in getArithmeticInstrCost()
200 { ISD::SRL, MVT::v16i8, 1 }, // psrlw. in getArithmeticInstrCost()
201 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. in getArithmeticInstrCost()
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DX86IntrinsicsInfo.h236 X86_INTRINSIC_DATA(avx2_psrlv_d, INTR_TYPE_2OP, ISD::SRL, 0),
237 X86_INTRINSIC_DATA(avx2_psrlv_d_256, INTR_TYPE_2OP, ISD::SRL, 0),
238 X86_INTRINSIC_DATA(avx2_psrlv_q, INTR_TYPE_2OP, ISD::SRL, 0),
239 X86_INTRINSIC_DATA(avx2_psrlv_q_256, INTR_TYPE_2OP, ISD::SRL, 0),
387 X86_INTRINSIC_DATA(avx512_mask_psrlv_d, INTR_TYPE_2OP_MASK, ISD::SRL, 0),
388 X86_INTRINSIC_DATA(avx512_mask_psrlv_q, INTR_TYPE_2OP_MASK, ISD::SRL, 0),
/external/llvm/test/CodeGen/Mips/
Dfcopysign-f32-f64.ll39 ; 64-DAG: srl $[[SRL:[0-9]+]], ${{[0-9]+}}, 31
40 ; 64-DAG: sll $[[SLL:[0-9]+]], $[[SRL]], 0
/external/llvm/test/CodeGen/SystemZ/
Dshift-09.ll25 ; Check that we use SRLK over SRL where useful.
35 ; Check that we use SRL over SRLK where possible.
Dshift-02.ll5 ; Check the low end of the SRL range.
14 ; Check the high end of the defined SRL range.
Dshift-10.ll69 ; Test that SRA gets replaced with SRL if the sign bit is the only one
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp617 if (InOp.getOpcode() == ISD::SRL && in SimplifyDemandedBits()
625 Opc = ISD::SRL; in SimplifyDemandedBits()
665 InnerOp.getOpcode() == ISD::SRL && in SimplifyDemandedBits()
692 case ISD::SRL: in SimplifyDemandedBits()
710 unsigned Opc = ISD::SRL; in SimplifyDemandedBits()
743 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), in SimplifyDemandedBits()
775 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, in SimplifyDemandedBits()
785 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, in SimplifyDemandedBits()
982 case ISD::SRL: in SimplifyDemandedBits()
986 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) in SimplifyDemandedBits()
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DLegalizeIntegerTypes.cpp78 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; in PromoteIntegerResult()
309 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), in PromoteIntRes_BSWAP()
636 return DAG.getNode(ISD::SRL, SDLoc(N), Res.getValueType(), Res, Amt); in PromoteIntRes_SRL()
735 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, in PromoteIntRes_XMULO()
868 case ISD::SRL: in PromoteIntegerOperand()
1317 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; in ExpandIntegerResult()
1388 DAG.getNode(ISD::SRL, DL, NVT, InL, in ExpandShiftByConstant()
1394 if (N->getOpcode() == ISD::SRL) { in ExpandShiftByConstant()
1399 Lo = DAG.getNode(ISD::SRL, DL, in ExpandShiftByConstant()
1407 DAG.getNode(ISD::SRL, DL, NVT, InL, in ExpandShiftByConstant()
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DLegalizeDAG.cpp391 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in ExpandUnalignedStore()
796 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value, in LegalizeStoreOps()
807 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value, in LegalizeStoreOps()
1305 case ISD::SRL: in LegalizeOp()
2489 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, in ExpandLegalINT_TO_FP()
2510 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst); in ExpandLegalINT_TO_FP()
2544 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, in ExpandLegalINT_TO_FP()
2699 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); in ExpandBSWAP()
2704 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); in ExpandBSWAP()
2705 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); in ExpandBSWAP()
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DDAGCombiner.cpp1059 else if (Opc == ISD::SRL) in PromoteIntShiftOp()
1329 case ISD::SRL: return visitSRL(N); in visit()
1422 case ISD::SRL: in combine()
2142 SDValue SRL = in visitSDIV() local
2143 DAG.getNode(ISD::SRL, SDLoc(N), VT, SGN, in visitSDIV()
2146 SDValue ADD = DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, SRL); in visitSDIV()
2147 AddToWorklist(SRL.getNode()); in visitSDIV()
2195 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, in visitUDIV()
2209 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, Add); in visitUDIV()
2353 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS()
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DLegalizeVectorOps.cpp277 case ISD::SRL: in LegalizeOp()
558 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt); in ExpandLoad()
935 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) in ExpandUINT_TO_FLOAT()
955 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord); in ExpandUINT_TO_FLOAT()
/external/llvm/lib/Target/ARM/
DARMSelectionDAGInfo.h27 case ISD::SRL: return ARM_AM::lsr; in getShiftOpcForNode()
/external/llvm/lib/Target/SystemZ/
DSystemZSelectionDAGInfo.cpp184 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i32, IPM, in addIPMSequence() local
186 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL, in addIPMSequence()
DSystemZInstrInfo.cpp454 MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI); in removeIPMBasedCompare() local
455 if (!SRL || !isShift(SRL, SystemZ::SRL, SystemZ::IPM_CC)) in removeIPMBasedCompare()
458 MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI); in removeIPMBasedCompare()
476 eraseIfDead(SRL, MRI); in removeIPMBasedCompare()
/external/valgrind/none/tests/mips64/
Dshift_instructions.c10 SRA, SRAV, SRL, SRLV enumerator
189 case SRL: in main()
/external/pcre/dist/sljit/
DsljitNativeSPARC_32.c71 …return push_inst(compiler, (op == SLJIT_MOV_SH ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst)); in emit_single_op()
130 FAIL_IF(push_inst(compiler, SRL | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst))); in emit_single_op()
DsljitNativeMIPS_32.c135 FAIL_IF(push_inst(compiler, SRL | T(src2) | DA(EQUAL_FLAG) | SH_IMM(31), EQUAL_FLAG)); in emit_single_op()
271 …return push_inst(compiler, SRL | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG) | SH_IMM(31), OVERFLOW_FLAG… in emit_single_op()
332 EMIT_SHIFT(SRL, SRLV); in emit_single_op()
/external/v8/src/mips/
Dconstants-mips.cc225 case SRL: in InstructionType()
/external/v8/src/mips64/
Dconstants-mips64.cc227 case SRL: in InstructionType()
/external/llvm/test/CodeGen/PowerPC/
Dload-shift-combine.ll4 ; load. Later the pre-increment load is combined with a subsequent SRL to
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h323 SHL, SRA, SRL, ROTL, ROTR, enumerator
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.h65 SHL, SRA, SRL enumerator
DMSP430ISelLowering.cpp97 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
100 setOperationAction(ISD::SRL, MVT::i16, Custom); in MSP430TargetLowering()
191 case ISD::SRL: in LowerOperation()
759 case ISD::SRL: in LowerShifts()
760 return DAG.getNode(MSP430ISD::SRL, dl, in LowerShifts()
771 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
/external/llvm/lib/Target/R600/
DR600ISelLowering.cpp1025 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift); in LowerSHLParts()
1026 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One); in LowerSHLParts()
1066 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift); in LowerSRXParts()
1067 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift); in LowerSRXParts()
1070 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift); in LowerSRXParts()
1279 return DAG.getNode(ISD::SRL, SDLoc(Ptr), Ptr.getValueType(), Ptr, in stackPtrToRegIndex()
1336 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr, in LowerSTORE()
1362 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), in LowerSTORE()
1491 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1536 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)), in LowerLOAD()
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp434 } else if (Opcode == ISD::SRL) { in isRotateAndMask()
481 Op0.getOperand(0).getOpcode() == ISD::SRL) { in SelectBitfieldInsert()
483 Op1.getOperand(0).getOpcode() != ISD::SRL) { in SelectBitfieldInsert()
489 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) { in SelectBitfieldInsert()
491 Op1.getOperand(0).getOpcode() != ISD::SRL) { in SelectBitfieldInsert()
502 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && in SelectBitfieldInsert()
516 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask && in SelectBitfieldInsert()
894 case ISD::SRL: in getValueBits()
1918 case ISD::SRL: in SelectBitPermutation()
2540 if (Val.getOpcode() == ISD::SRL && in Select()
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