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Searched refs:mtc1 (Results 1 – 25 of 90) sorted by relevance

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/external/valgrind/none/tests/mips64/
D	move_instructions.stdout.exp-BE	1 mtc1, mov.s, mfc1 :: mem: 0x0 out: 0x0 3 mtc1, mov.s, mfc1 :: mem: 0x12bd6aa out: 0x12bd6aa 5 mtc1, mov.s, mfc1 :: mem: 0x0 out: 0x0 7 mtc1, mov.s, mfc1 :: mem: 0x7e876382d2ab13 out: 0xffffffff82d2ab13 9 mtc1, mov.s, mfc1 :: mem: 0x9823b6e out: 0x9823b6e 11 mtc1, mov.s, mfc1 :: mem: 0x976d6e9ac31510f3 out: 0xffffffffc31510f3 13 mtc1, mov.s, mfc1 :: mem: 0xd4326d9 out: 0xd4326d9 15 mtc1, mov.s, mfc1 :: mem: 0xb7746d775ad6a5fb out: 0x5ad6a5fb 17 mtc1, mov.s, mfc1 :: mem: 0x130476dc out: 0x130476dc 19 mtc1, mov.s, mfc1 :: mem: 0x42b0c0a28677b502 out: 0xffffffff8677b502 [all …]
D	move_instructions.stdout.exp-LE	1 mtc1, mov.s, mfc1 :: mem: 0x0 out: 0x0 3 mtc1, mov.s, mfc1 :: mem: 0x12bd6aa out: 0x12bd6aa 5 mtc1, mov.s, mfc1 :: mem: 0x0 out: 0x0 7 mtc1, mov.s, mfc1 :: mem: 0x7e876382d2ab13 out: 0xffffffff82d2ab13 9 mtc1, mov.s, mfc1 :: mem: 0x9823b6e out: 0x9823b6e 11 mtc1, mov.s, mfc1 :: mem: 0x976d6e9ac31510f3 out: 0xffffffffc31510f3 13 mtc1, mov.s, mfc1 :: mem: 0xd4326d9 out: 0xd4326d9 15 mtc1, mov.s, mfc1 :: mem: 0xb7746d775ad6a5fb out: 0x5ad6a5fb 17 mtc1, mov.s, mfc1 :: mem: 0x130476dc out: 0x130476dc 19 mtc1, mov.s, mfc1 :: mem: 0x42b0c0a28677b502 out: 0xffffffff8677b502 [all …]
/external/llvm/test/CodeGen/Mips/
D	fmadd1.ll	`25 ; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]] 28 ; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]] 31 ; 32R2: mtc1 $6, $[[T0:f[0-9]+]] 33 ; 32R2: mtc1 $zero, $[[T2:f[0-9]+]] 36 ; 32R6-DAG: mtc1 $6, $[[T0:f[0-9]+]] 39 ; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] 43 ; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]] 47 ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]] 52 ; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] 65 ; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]] [all …]`
D	fpxx.ll	`29 ; 32-NOFPXX: mtc1 $4, $f0 30 ; 32-NOFPXX: mtc1 $5, $f1 37 ; 32R2-NOFPXX: mtc1 $4, $f0 40 ; 32R2-FPXX: mtc1 $4, $f0 54 ; 32-NOFPXX: mtc1 $6, $f0 55 ; 32-NOFPXX: mtc1 $7, $f1 62 ; 32R2-NOFPXX: mtc1 $6, $f0 65 ; 32R2-FPXX: mtc1 $6, $f0 78 ; 32-NOFPXX: mtc1 $6, $f0 79 ; 32-NOFPXX: mtc1 $7, $f1 [all …]`
D	select.ll	`135 ; 32-DAG: mtc1 $5, $[[F0:f[0-9]+]] 136 ; 32-DAG: mtc1 $6, $[[F1:f0]] 139 ; 32R2-DAG: mtc1 $5, $[[F0:f[0-9]+]] 140 ; 32R2-DAG: mtc1 $6, $[[F1:f0]] 143 ; 32R6-DAG: mtc1 $5, $[[F0:f[0-9]+]] 144 ; 32R6-DAG: mtc1 $6, $[[F1:f[0-9]+]] 146 ; 32R6: mtc1 $[[T0]], $[[CC:f0]] 156 ; 64R6: mtc1 $[[T0]], $[[CC:f0]] 168 ; 32-DAG: mtc1 $6, $[[F0:f[1-3][02468]+]] 169 ; 32-DAG: mtc1 $7, $[[F0H:f[1-3][13579]+]] [all …]`
D	fp64a.ll	`3 ; use mfc1/mtc1 to move the bottom 32-bits (because the hardware will redirect 34 ; 32R2-NO-FP64A-LE: mtc1 $4, $f0 38 ; 32R2-NO-FP64A-BE: mtc1 $5, $f0 55 ; 32R2-NO-FP64A-LE: mtc1 $6, $f0 58 ; 32R2-NO-FP64A-BE: mtc1 $7, $f0 75 ; 32R2-NO-FP64A-LE: mtc1 $6, $f0 78 ; 32R2-NO-FP64A-BE: mtc1 $7, $f0 95 ; 32R2-NO-FP64A-LE: mtc1 $6, $f0 98 ; 32R2-NO-FP64A-BE: mtc1 $7, $f0 116 ; 32R2-NO-FP64A-LE-DAG: mtc1 $4, $[[T0:f[0-9]+]] [all …]`
D	mno-ldc1-sdc1.ll	`57 ; 32R1-LE-PIC-DAG: mtc1 $[[R0]], $f0 58 ; 32R1-LE-PIC-DAG: mtc1 $[[R1]], $f1 62 ; 32R2-LE-PIC-DAG: mtc1 $[[R0]], $f0 67 ; 32R6-LE-PIC-DAG: mtc1 $[[R0]], $f0 74 ; 32R1-LE-STATIC-DAG: mtc1 $[[R1]], $f0 75 ; 32R1-LE-STATIC-DAG: mtc1 $[[R3]], $f1 81 ; 32R2-LE-STATIC-DAG: mtc1 $[[R1]], $f0 88 ; 32R6-LE-STATIC-DAG: mtc1 $[[R1]], $f0 93 ; 32R1-BE-PIC-DAG: mtc1 $[[R1]], $f0 94 ; 32R1-BE-PIC-DAG: mtc1 $[[R0]], $f1 [all …]`
D	2013-11-18-fp64-const0.ll	`13 ; CHECK-FP32: mtc1 $zero, $f{{[0-3][02468]}} 14 ; CHECK-FP32: mtc1 $zero, $f{{[0-3][13579]}} 16 ; CHECK-FP64: mtc1 $zero, $f{{[0-9]+}} 17 ; CHECK-FP64-NOT: mtc1 $zero,`
D	hf16call32.ll	`756 ; stel: mtc1 $4,$f12 769 ; stel: mtc1 $4,$f12 770 ; stel: mtc1 $5,$f13 779 ; stel: mtc1 $4,$f12 780 ; stel: mtc1 $5,$f14 789 ; stel: mtc1 $4,$f12 790 ; stel: mtc1 $6,$f14 791 ; stel: mtc1 $7,$f15 800 ; stel: mtc1 $4,$f12 801 ; stel: mtc1 $5,$f13 [all …]`
D	int-to-float-conversion.ll	`9 ; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]] 19 ; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]] 22 ; 64: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]`
D	buildpairextractelementf64.ll	`12 ; NO-MFHC1: mtc1 13 ; NO-MFHC1: mtc1 15 ; HAS-MFHC1-DAG: mtc1`
D	fcopysign.ll	`16 ; 32: mtc1 $[[OR]], $f1 49 ; 32: mtc1 $[[OR]], $f0 53 ; 32R2: mtc1 $[[INS]], $f0`
D	fcopysign-f32-f64.ll	`19 ; 64: mtc1 $[[OR]], $f0 23 ; 64R2: mtc1 $[[INS]], $f0`
D	analyzebranch.ll	`16 ; 32-GPR: mtc1 $zero, $[[Z:f[0-9]]] 49 ; GPR: mtc1 $zero, $[[Z:f[0-9]]]`
D	2008-08-04-Bitconvert.ll	`5 ; CHECK: mtc1`
D	constantfp0.ll	`5 ; CHECK: mtc1 $zero, $f[[R0:[0-9]+]]`
/external/llvm/test/CodeGen/Mips/Fast-ISel/
D	callabi.ll	`135 ; CHECK: mtc1 $[[REG_FPCONST]], $f12 151 ; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12 154 ; CHECK-DAG: mtc1 $[[REG_FPCONST_3]], $f14 170 ; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12 188 ; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12 206 ; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12 230 ; mips32-DAG: mtc1 $[[REG_FPCONST_4]], $f12 231 ; mips32-DAG: mtc1 $[[REG_FPCONST_2]], $f13 239 ; mips32r2-DAG: mtc1 $[[REG_FPCONST_4]], $f12 259 ; mips32-DAG: mtc1 $[[REG_FPCONST_4]], $f12 [all …]`
D	simplestorefp1.ll	`21 ; CHECK: mtc1 $[[REG2]], $f[[REG3:[0-9]+]] 37 ; mips32r2: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]] 46 ; mips32: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]] 47 ; mips32: mtc1 $[[REG2a]], $f{{[0-9]+}}`
/external/valgrind/none/tests/mips32/
D	MoveIns.stdout.exp-BE	`30 mtc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266 31 mtc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666 32 mtc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000 33 mtc1 $t4, $f3 :: fs 0.000000, rt 0x0 34 mtc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000 35 mtc1 $t6, $f5 :: fs 0.000000, rt 0x0 36 mtc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b 37 mtc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a 38 mtc1 $v1, $f8 :: fs nan, rt 0xffffffff 39 mtc1 $s0, $f9 :: fs nan, rt 0xffffffff [all …]`
D	MoveIns.stdout.exp	`30 mtc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266 31 mtc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666 32 mtc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000 33 mtc1 $t4, $f3 :: fs 0.000000, rt 0x0 34 mtc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000 35 mtc1 $t6, $f5 :: fs 0.000000, rt 0x0 36 mtc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b 37 mtc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a 38 mtc1 $v1, $f8 :: fs nan, rt 0xffffffff 39 mtc1 $s0, $f9 :: fs nan, rt 0xffffffff [all …]`
/external/llvm/test/CodeGen/Mips/llvm-ir/
D	select.ll	`172 ; M2: mtc1 $6, $f0 176 ; M2: mtc1 $5, $f0 179 ; CMOV-32: mtc1 $6, $f0 180 ; CMOV-32: mtc1 $5, $f1 184 ; SEL-32: mtc1 $5, $[[F0:f[0-9]+]] 185 ; SEL-32: mtc1 $6, $[[F1:f[0-9]+]] 186 ; SEL-32: mtc1 $4, $f0 193 ; SEL-64: mtc1 $4, $f0 217 ; SEL-32: mtc1 $6, $f0 224 ; SEL-64: mtc1 $6, $f0 [all …]`
D	ret.ll	`155 ; NO-MTHC1-DAG: mtc1 $zero, $f0 157 ; MTHC1-DAG: mtc1 $zero, $f0 184 ; NO-MTHC1-DAG: mtc1 $zero, $f0 185 ; NO-MTHC1-DAG: mtc1 $zero, $f1 187 ; MTHC1-DAG: mtc1 $zero, $f0`
/external/llvm/test/CodeGen/Mips/cconv/
D	arguments-hard-float-varargs.ll	`49 ; O32BE-DAG: mtc1 $5, [[FTMP1:\$f[0-9][02468]+]] 50 ; O32BE-DAG: mtc1 $4, [[FTMP2:\$f[0-9][13579]+]] 51 ; O32LE-DAG: mtc1 $4, [[FTMP1:\$f[0-9][02468]+]] 52 ; O32LE-DAG: mtc1 $5, [[FTMP2:\$f[0-9][13579]+]]`
D	arguments-hard-float.ll	`178 ; O32LE-DAG: mtc1 $6, [[F1:\$f[0-9][02468]+]] 179 ; O32LE-DAG: mtc1 $7, [[F2:\$f[0-9][13579]+]] 180 ; O32BE-DAG: mtc1 $6, [[F2:\$f[0-9][13579]+]] 181 ; O32BE-DAG: mtc1 $7, [[F1:\$f[0-9][02468]+]]`
/external/v8/test/cctest/
D	test-assembler-mips.cc	`284 __ mtc1(t0, f14); in TEST() local 360 __ mtc1(t0, f6); in TEST() local 361 __ mtc1(t1, f7); in TEST() local 362 __ mtc1(t2, f4); in TEST() local 363 __ mtc1(t3, f5); in TEST() local 371 __ mtc1(t0, f6); in TEST() local 373 __ mtc1(t2, f4); in TEST() local 434 __ mtc1(t0, f12); in TEST() local 439 __ mtc1(t1, f14); in TEST() local 795 __ mtc1(t0, f8); // f8 has a 32-bits word. in TEST() local`

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