| /external/llvm/lib/Target/ARM/ |
| D | ThumbRegisterInfo.cpp | 127 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmInReg() argument
134 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg()
146 assert(BaseReg == ARM::SP && "Unexpected!"); in emitThumbRegPlusImmInReg()
170 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
172 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg()
183 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmediate() argument
214 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
226 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
232 } else if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
235 } else if (isARMLowRegister(BaseReg)) { in emitThumbRegPlusImmediate()
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| D | Thumb2InstrInfo.cpp | 218 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitT2RegPlusImmediate() argument
221 if (NumBytes == 0 && DestReg != BaseReg) { in emitT2RegPlusImmediate()
223 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
233 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
255 .addReg(BaseReg) in emitT2RegPlusImmediate()
266 .addReg(BaseReg) in emitT2RegPlusImmediate()
278 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
281 .addReg(BaseReg).setMIFlags(MIFlags)); in emitT2RegPlusImmediate()
282 BaseReg = ARM::SP; in emitT2RegPlusImmediate()
287 if (BaseReg == ARM::SP) { in emitT2RegPlusImmediate()
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| D | ARMBaseRegisterInfo.h | 142 unsigned BaseReg, int FrameIdx,
144 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
146 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
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| D | ARMBaseRegisterInfo.cpp | 558 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister() argument
573 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
575 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
582 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex() argument
601 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
604 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
610 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, in isFrameOffsetLegal() argument
654 NumBits = (BaseReg == ARM::SP ? 8 : 5); in isFrameOffsetLegal()
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| D | ARMLoadStoreOptimizer.cpp | 1494 unsigned BaseReg, bool BaseKill, bool BaseUndef, in InsertLDR_STR() argument
1502 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1508 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1521 unsigned BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp() local
1529 bool Errata602117 = EvenReg == BaseReg && in FixInvalidRegPairOp()
1562 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
1569 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
1592 (TRI->regsOverlap(EvenReg, BaseReg))) { in FixInvalidRegPairOp()
1593 assert(!TRI->regsOverlap(OddReg, BaseReg)); in FixInvalidRegPairOp()
1596 BaseReg, false, BaseUndef, false, OffUndef, in FixInvalidRegPairOp()
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| D | Thumb2SizeReduction.cpp | 421 unsigned BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
422 assert(isARMLowRegister(BaseReg)); in ReduceLoadStore()
428 if (MI->getOperand(i).getReg() == BaseReg) { in ReduceLoadStore()
450 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
451 if (BaseReg != ARM::SP) in ReduceLoadStore()
463 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
464 if (BaseReg == ARM::SP && in ReduceLoadStore()
469 } else if (!isARMLowRegister(BaseReg) || in ReduceLoadStore()
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| D | ARMBaseInstrInfo.h | 86 RegSubRegPair &BaseReg,
470 unsigned DestReg, unsigned BaseReg, int NumBytes,
476 unsigned DestReg, unsigned BaseReg, int NumBytes,
481 unsigned DestReg, unsigned BaseReg,
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| /external/llvm/lib/CodeGen/ |
| D | LocalStackSlotAllocation.cpp | 255 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg() argument
264 return TRI->isFrameOffsetLegal(MI, BaseReg, Offset); in lookupCandidateBaseReg()
330 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
366 if (UsedBaseReg && lookupCandidateBaseReg(BaseReg, BaseOffset, in insertFrameReferenceRegisters()
369 DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n"); in insertFrameReferenceRegisters()
387 BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
396 BaseReg = Fn.getRegInfo().createVirtualRegister(RC); in insertFrameReferenceRegisters()
398 DEBUG(dbgs() << " Materializing base register " << BaseReg << in insertFrameReferenceRegisters()
404 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx, in insertFrameReferenceRegisters()
415 assert(BaseReg != 0 && "Unable to allocate virtual base register!"); in insertFrameReferenceRegisters()
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| D | ImplicitNullChecks.cpp | 327 unsigned BaseReg, Offset; in analyzeBlockForNullChecks() local
328 if (TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI)) in analyzeBlockForNullChecks()
329 if (MI->mayLoad() && !MI->isPredicable() && BaseReg == PointerReg && in analyzeBlockForNullChecks()
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| D | CodeGenPrepare.cpp | 2026 Value *BaseReg; member
2028 ExtAddrMode() : BaseReg(nullptr), ScaledReg(nullptr) {} in ExtAddrMode()
2033 return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) && in operator ==()
2062 if (BaseReg) { in print()
2065 BaseReg->printAsOperand(OS, /*PrintType=*/false); in print()
3233 AddrMode.BaseReg = AddrInst->getOperand(0); in matchOperationAddr()
3246 AddrMode.BaseReg = AddrInst->getOperand(0); in matchOperationAddr()
3380 AddrMode.BaseReg = Addr; in matchAddr()
3385 AddrMode.BaseReg = nullptr; in matchAddr()
3538 Value *BaseReg = AMAfter.BaseReg, *ScaledReg = AMAfter.ScaledReg; in isProfitableToFoldIntoAddressingMode() local
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 266 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anon720aab8e0111::X86AsmParser::IntelExprStateMachine
276 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0), in IntelExprStateMachine()
280 unsigned getBaseReg() { return BaseReg; } in getBaseReg()
386 if (!BaseReg) { in onPlus()
387 BaseReg = TmpReg; in onPlus()
423 if (!BaseReg) { in onMinus()
424 BaseReg = TmpReg; in onMinus()
602 if (!BaseReg) { in onRBrac()
603 BaseReg = TmpReg; in onRBrac()
713 CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
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| D | X86Operand.h | 55 unsigned BaseReg; member
117 return Mem.BaseReg; in getMemBaseReg()
502 Res->Mem.BaseReg = 0;
516 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
521 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
529 Res->Mem.BaseReg = BaseReg;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64StorePairSuppress.cpp | 143 unsigned BaseReg; in runOnMachineFunction() local
145 if (TII->getMemOpBaseRegImmOfs(&MI, BaseReg, Offset, TRI)) { in runOnMachineFunction()
146 if (PrevBaseReg == BaseReg) { in runOnMachineFunction()
155 PrevBaseReg = BaseReg; in runOnMachineFunction()
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| D | AArch64LoadStoreOptimizer.cpp | 121 unsigned BaseReg, int Offset);
880 unsigned BaseReg = getLdStBaseOp(FirstMI).getReg(); in findMatchingInsn() local
890 if (FirstMI->modifiesRegister(BaseReg, TRI)) in findMatchingInsn()
946 if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) || in findMatchingInsn()
1032 if (ModifiedRegs[BaseReg]) in findMatchingInsn()
1105 unsigned BaseReg, int Offset) { in isMatchingUpdateInsn() argument
1124 if (MI->getOperand(0).getReg() != BaseReg || in isMatchingUpdateInsn()
1125 MI->getOperand(1).getReg() != BaseReg) in isMatchingUpdateInsn()
1163 unsigned BaseReg = getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnForward() local
1177 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg)) in findMatchingUpdateInsnForward()
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| D | AArch64RegisterInfo.h | 77 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
79 void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
82 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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| D | AArch64RegisterInfo.cpp | 306 unsigned BaseReg, in isFrameOffsetLegal() argument
317 unsigned BaseReg, in materializeFrameBaseRegister() argument
329 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
332 BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
338 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex() argument
350 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
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| D | AArch64InstrInfo.h | 93 bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
97 bool getMemOpBaseRegImmOfsWidth(MachineInstr *LdSt, unsigned &BaseReg,
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is16BitMemOperand() local
64 if (is16BitMode(STI) && BaseReg.getReg() == 0 && in Is16BitMemOperand()
67 if ((BaseReg.getReg() != 0 && in Is16BitMemOperand()
68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || in Is16BitMemOperand()
226 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is32BitMemOperand() local
229 if ((BaseReg.getReg() != 0 && in Is32BitMemOperand()
230 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || in Is32BitMemOperand()
241 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is64BitMemOperand() local
244 if ((BaseReg.getReg() != 0 && in Is64BitMemOperand()
245 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || in Is64BitMemOperand()
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86ATTInstPrinter.cpp | 189 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference() local
204 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference()
211 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference()
213 if (BaseReg.getReg()) in printMemReference()
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| D | X86IntelInstPrinter.cpp | 159 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference() local
174 if (BaseReg.getReg()) { in printMemReference()
193 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printMemReference()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.h | 127 unsigned BaseReg, int FrameIdx,
129 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
131 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
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| D | PPCRegisterInfo.cpp | 980 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister() argument
994 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
996 BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
1000 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex() argument
1009 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false); in resolveFrameIndex()
1020 MRI.constrainRegClass(BaseReg, in resolveFrameIndex()
1025 unsigned BaseReg, in isFrameOffsetLegal() argument
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| /external/llvm/lib/Target/X86/ |
| D | X86AsmPrinter.cpp | 245 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printLeaMemReference() local
250 bool HasBaseReg = BaseReg.getReg() != 0; in printLeaMemReference()
252 BaseReg.getReg() == X86::RIP) in printLeaMemReference()
310 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printIntelMemReference() local
325 if (BaseReg.getReg()) { in printIntelMemReference()
343 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printIntelMemReference()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 122 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange() local
123 emitMask(BaseReg, LoadStoreStackMaskReg, STI); in sandboxLoadStoreStackChange()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 822 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister() argument
830 virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex() argument
837 virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, in isFrameOffsetLegal() argument
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