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Searched refs:GPR32RegClass (Results 1 – 17 of 17) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp265 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp()
284 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in fastMaterializeAlloca()
298 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeInt()
335 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass); in materializeFP()
341 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass); in materializeFP()
343 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass); in materializeFP()
354 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeGV()
376 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeExternalCallSym()
596 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
602 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
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DMipsMachineFunction.cpp50 : &Mips::GPR32RegClass; in getGlobalBaseReg()
71 : &Mips::GPR32RegClass; in createEhDataRegsFI()
83 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in createISRRegFI()
DMipsOptionRecord.h46 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
64 const MCRegisterClass *GPR32RegClass; variable
DMipsSERegisterInfo.cpp60 return &Mips::GPR32RegClass; in intRegClass()
183 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in eliminateFI()
DMipsSEFrameLowering.cpp295 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64()
360 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass; in expandExtractElementF64()
398 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitPrologue()
569 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass; in emitInterruptPrologueStub()
698 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitEpilogue()
733 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass; in emitInterruptEpilogueStub()
872 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in determineCalleeSaves()
886 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in determineCalleeSaves()
DMipsSEInstrInfo.cpp86 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
87 if (Mips::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
114 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg. in copyPhysReg()
189 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
262 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
459 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in loadImmediate()
DMipsSubtarget.cpp135 &Mips::GPR64RegClass : &Mips::GPR32RegClass); in getCriticalPathRCs()
DMips16InstrInfo.cpp68 Mips::GPR32RegClass.contains(SrcReg)) in copyPhysReg()
70 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
DMipsRegisterInfo.cpp55 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
DMipsAsmPrinter.cpp257 unsigned CPURegSize = Mips::GPR32RegClass.getSize(); in printSavedRegsBitmask()
276 } else if (Mips::GPR32RegClass.contains(Reg)) in printSavedRegsBitmask()
DMipsSEISelDAGToDAG.cpp143 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
DMipsSEISelLowering.cpp42 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); in MipsSETargetLowering()
2927 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in emitBPOSGE32()
2992 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in emitMSACBranchPseudo()
3220 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitINSERT_DF_VIDX()
DMipsISelLowering.cpp3439 return std::make_pair(0U, &Mips::GPR32RegClass); in getRegForInlineAsmConstraint()
3442 return std::make_pair(0U, &Mips::GPR32RegClass); in getRegForInlineAsmConstraint()
3466 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); in getRegForInlineAsmConstraint()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp345 : &AArch64::GPR32RegClass; in materializeInt()
378 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP()
1261 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rr()
1304 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_ri()
1346 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rs()
1387 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rx()
1684 RC = &AArch64::GPR32RegClass; in emitLogicalOp_rs()
1790 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
1795 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
1800 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
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DAArch64InstrInfo.cpp492 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) { in insertSelect()
493 RC = &AArch64::GPR32RegClass; in insertSelect()
1141 return (AArch64::GPR32RegClass.contains(DstReg) || in isGPRCopy()
1798 AArch64::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
1803 if (AArch64::GPR32RegClass.contains(DestReg) && in copyPhysReg()
1860 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass); in storeRegToStackSlot()
1958 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass); in loadRegFromStackSlot()
2726 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
2741 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
2763 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
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DAArch64ISelLowering.cpp2438 RC = &AArch64::GPR32RegClass; in LowerFormalArguments()
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsOptionRecord.cpp79 if (GPR32RegClass->contains(CurrentSubReg) || in SetPhysRegUsed()