Searched refs:GPR64RegClass (Results 1 – 18 of 18) sorted by relevance
47 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()65 const MCRegisterClass *GPR64RegClass; variable
49 ? &Mips::GPR64RegClass in getGlobalBaseReg()70 ? &Mips::GPR64RegClass in createEhDataRegsFI()
63 return &Mips::GPR64RegClass; in intRegClass()183 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in eliminateFI()
142 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg. in copyPhysReg()143 if (Mips::GPR64RegClass.contains(SrcReg)) in copyPhysReg()152 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg. in copyPhysReg()191 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in storeRegToStack()264 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in loadRegFromStack()459 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in loadImmediate()
135 &Mips::GPR64RegClass : &Mips::GPR32RegClass); in getCriticalPathRCs()
398 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitPrologue()698 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitEpilogue()872 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in determineCalleeSaves()886 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in determineCalleeSaves()
55 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
143 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
45 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); in MipsSETargetLowering()3220 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitINSERT_DF_VIDX()
3444 return std::make_pair(0U, &Mips::GPR64RegClass); in getRegForInlineAsmConstraint()3468 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); in getRegForInlineAsmConstraint()
760 if (AArch64::GPR64RegClass.contains(Reg1)) { in spillCalleeSavedRegisters()761 assert(AArch64::GPR64RegClass.contains(Reg2) && in spillCalleeSavedRegisters()833 if (AArch64::GPR64RegClass.contains(Reg1)) { in restoreCalleeSavedRegisters()834 assert(AArch64::GPR64RegClass.contains(Reg2) && in restoreCalleeSavedRegisters()914 assert((AArch64::GPR64RegClass.contains(OddReg) && in determineCalleeSaves()915 AArch64::GPR64RegClass.contains(EvenReg)) ^ in determineCalleeSaves()926 if (AArch64::GPR64RegClass.contains(OddReg)) { in determineCalleeSaves()952 if (AArch64::GPR64RegClass.contains(OddReg)) { in determineCalleeSaves()1005 const TargetRegisterClass *RC = &AArch64::GPR64RegClass; in determineCalleeSaves()
161 return &AArch64::GPR64RegClass; in getPointerRegClass()167 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV. in getCrossCopyRegClass()394 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); in eliminateFrameIndex()
344 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass in materializeInt()378 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP()436 ResultReg = createResultReg(&AArch64::GPR64RegClass); in materializeGV()1261 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rr()1304 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_ri()1346 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rs()1387 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rx()1688 RC = &AArch64::GPR64RegClass; in emitLogicalOp_rs()1790 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()1795 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()[all …]
488 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) { in insertSelect()489 RC = &AArch64::GPR64RegClass; in insertSelect()1142 AArch64::GPR64RegClass.contains(DstReg)); in isGPRCopy()1785 AArch64::GPR64RegClass.contains(SrcReg)) { in copyPhysReg()1790 if (AArch64::GPR64RegClass.contains(DestReg) && in copyPhysReg()1811 assert(AArch64::GPR64RegClass.contains(SrcReg) && "Invalid NZCV copy"); in copyPhysReg()1820 assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy"); in copyPhysReg()1870 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass); in storeRegToStackSlot()1968 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass); in loadRegFromStackSlot()2105 MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass); in foldMemoryOperandImpl()[all …]
117 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()118 return AArch64::GPR64RegClass.contains(Reg); in isGPR64()
117 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass); in setRegister()
2440 RC = &AArch64::GPR64RegClass; in LowerFormalArguments()2589 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass); in saveVarArgRegisters()3279 if (AArch64::GPR64RegClass.contains(*I)) in LowerReturn()4388 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass); in LowerRETURNADDR()10041 if (AArch64::GPR64RegClass.contains(*I)) in insertCopiesSplitCSR()10042 RC = &AArch64::GPR64RegClass; in insertCopiesSplitCSR()
80 GPR64RegClass->contains(CurrentSubReg)) in SetPhysRegUsed()