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/external/llvm/lib/Target/Mips/
DMicroMipsInstrFormats.td35 field bits<16> Inst;
49 bits<16> Inst;
51 let Inst{15-10} = 0x01;
52 let Inst{9-7} = rd;
53 let Inst{6-4} = rt;
54 let Inst{3-1} = rs;
55 let Inst{0} = funct;
63 bits<16> Inst;
65 let Inst{15-10} = funct;
66 let Inst{9-7} = rd;
[all …]
DMicroMips32r6InstrFormats.td28 bits<16> Inst;
30 let Inst{15-10} = 0x33;
31 let Inst{9-0} = offset;
38 bits<16> Inst;
40 let Inst{15-10} = op;
41 let Inst{9-7} = rs;
42 let Inst{6-0} = offset;
48 bits<16> Inst;
50 let Inst{15-10} = 0x11;
51 let Inst{9-5} = rs;
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DMipsMSAInstrFormats.td13 let Inst{31-26} = 0b011110;
17 let Inst{31-26} = 0b010001;
21 let Inst{31-26} = 0b000000;
35 let Inst{25-23} = major;
36 let Inst{22-19} = 0b1110;
37 let Inst{18-16} = m;
38 let Inst{15-11} = ws;
39 let Inst{10-6} = wd;
40 let Inst{5-0} = minor;
48 let Inst{25-23} = major;
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DMipsInstrFormats.td75 field bits<32> Inst;
85 let Inst{31-26} = Opcode;
156 let Inst{25-21} = rs;
157 let Inst{20-16} = rt;
158 let Inst{15-11} = rd;
159 let Inst{10-6} = shamt;
160 let Inst{5-0} = funct;
176 let Inst{25-21} = rs;
177 let Inst{20-16} = rt;
178 let Inst{15-0} = imm16;
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DMicroMipsDSPInstrFormats.td30 let Inst{31-26} = 0b000000;
31 let Inst{25-21} = rt;
32 let Inst{20-16} = rs;
33 let Inst{15-11} = rd;
34 let Inst{10-0} = op;
41 let Inst{31-26} = 0b000000;
42 let Inst{25-21} = rt;
43 let Inst{20-16} = rs;
44 let Inst{15-6} = op;
45 let Inst{5-0} = 0b111100;
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DMips32r6InstrFormats.td181 bits<32> Inst;
183 let Inst{31-26} = OPGROUP_AUI.Value;
184 let Inst{25-21} = rs;
185 let Inst{20-16} = rt;
186 let Inst{15-0} = imm;
190 let Inst{31-26} = OPGROUP_DAUI.Value;
196 bits<32> Inst;
198 let Inst{31-26} = OPGROUP_REGIMM.Value;
199 let Inst{25-21} = 0b00000;
200 let Inst{20-16} = OPCODE5_BGEZAL.Value;
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DMipsDSPInstrFormats.td69 let Inst{25-21} = rs;
70 let Inst{20-16} = rt;
71 let Inst{15-11} = rd;
72 let Inst{10-6} = op;
73 let Inst{5-0} = 0b010000;
82 let Inst{25-21} = rs;
83 let Inst{20-16} = 0;
84 let Inst{15-11} = rd;
85 let Inst{10-6} = op;
86 let Inst{5-0} = 0b010000;
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DMicroMips64r6InstrFormats.td19 bits<32> Inst;
21 let Inst{31-26} = 0b111100;
22 let Inst{25-21} = rt;
23 let Inst{20-16} = rs;
24 let Inst{15-0} = imm;
31 bits<32> Inst;
33 let Inst{31-26} = 0b010000;
34 let Inst{25-21} = funct;
35 let Inst{20-16} = rs;
36 let Inst{15-0} = imm;
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DMips16InstrFormats.td59 field bits<16> Inst;
63 let Inst{15-11} = Opcode;
76 field bits<32> Inst;
86 let Inst{31-27} = 0b11110;
111 let Inst{10-0} = imm11;
127 let Inst{10-8} = rx;
128 let Inst{7-0} = imm8;
146 let Inst{10-8} = rx;
147 let Inst{7-5} = ry;
148 let Inst{4-0} = funct;
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/external/llvm/lib/Target/AMDGPU/
DVIInstrFormats.td23 let Inst{7-0} = offset0;
24 let Inst{15-8} = offset1;
25 let Inst{16} = gds;
26 let Inst{24-17} = op;
27 let Inst{31-26} = 0x36; //encoding
28 let Inst{39-32} = addr;
29 let Inst{47-40} = data0;
30 let Inst{55-48} = data1;
31 let Inst{63-56} = vdst;
47 let Inst{11-0} = offset;
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DSIInstrFormats.td81 field bits<32> Inst;
86 field bits<64> Inst;
159 let Inst{7-0} = ssrc0;
160 let Inst{15-8} = op;
161 let Inst{22-16} = sdst;
162 let Inst{31-23} = 0x17d; //encoding;
170 let Inst{7-0} = ssrc0;
171 let Inst{15-8} = ssrc1;
172 let Inst{22-16} = sdst;
173 let Inst{29-23} = op;
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/external/llvm/lib/Target/XCore/Disassembler/
DXCoreDisassembler.cpp76 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
81 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
86 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
89 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
92 static DecodeStatus Decode2RInstruction(MCInst &Inst,
97 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
102 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
107 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
112 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
117 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
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/external/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp49 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, in decodeRegisterClass() argument
55 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
59 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGR32BitRegisterClass() argument
62 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16); in DecodeGR32BitRegisterClass()
65 static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGRH32BitRegisterClass() argument
68 return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16); in DecodeGRH32BitRegisterClass()
71 static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGR64BitRegisterClass() argument
74 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16); in DecodeGR64BitRegisterClass()
77 static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGR128BitRegisterClass() argument
80 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16); in DecodeGR128BitRegisterClass()
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/external/llvm/lib/Target/PowerPC/
DPPCInstrFormats.td16 field bits<32> Inst;
23 let Inst{0-5} = opcode;
71 field bits<64> Inst;
78 let Inst{0-5} = opcode1;
79 let Inst{32-37} = opcode2;
109 let Inst{6-29} = LI;
110 let Inst{30} = aa;
111 let Inst{31} = lk;
125 let Inst{6-10} = BIBO{4-0};
126 let Inst{11-15} = BI;
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/external/llvm/lib/Target/Hexagon/
DHexagonIsetDx.td23 let Inst{12-10} = 0b111;
24 let Inst{8} = 0b0;
25 let Inst{4-3} = 0b01;
26 let Inst{2-0} = Rdd;
27 let Inst{6-5} = u2;
37 let Inst{12-6} = 0b1111111;
38 let Inst{2-0} = 0b101;
47 let Inst{12-6} = 0b1111100;
48 let Inst{2} = 0b0;
58 let Inst{12-6} = 0b1111101;
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/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp67 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
72 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
77 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
82 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
87 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
92 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
97 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
102 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
107 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
112 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
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/external/llvm/lib/Transforms/Scalar/
DEarlyCSE.cpp54 Instruction *Inst; member
56 SimpleValue(Instruction *I) : Inst(I) { in SimpleValue()
61 return Inst == DenseMapInfo<Instruction *>::getEmptyKey() || in isSentinel()
62 Inst == DenseMapInfo<Instruction *>::getTombstoneKey(); in isSentinel()
65 static bool canHandle(Instruction *Inst) { in canHandle()
67 if (CallInst *CI = dyn_cast<CallInst>(Inst)) in canHandle()
69 return isa<CastInst>(Inst) || isa<BinaryOperator>(Inst) || in canHandle()
70 isa<GetElementPtrInst>(Inst) || isa<CmpInst>(Inst) || in canHandle()
71 isa<SelectInst>(Inst) || isa<ExtractElementInst>(Inst) || in canHandle()
72 isa<InsertElementInst>(Inst) || isa<ShuffleVectorInst>(Inst) || in canHandle()
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DSink.cpp60 bool AllUsesDominatedByBlock(Instruction *Inst, BasicBlock *BB) const;
61 bool IsAcceptableTarget(Instruction *Inst, BasicBlock *SuccToSinkTo) const;
76 bool Sinking::AllUsesDominatedByBlock(Instruction *Inst, in AllUsesDominatedByBlock() argument
82 for (Use &U : Inst->uses()) { in AllUsesDominatedByBlock()
137 Instruction *Inst = &*I; // The instruction to sink. in ProcessBlock() local
145 if (isa<DbgInfoIntrinsic>(Inst)) in ProcessBlock()
148 if (SinkInstruction(Inst, Stores)) in ProcessBlock()
157 static bool isSafeToMove(Instruction *Inst, AliasAnalysis *AA, in isSafeToMove() argument
160 if (Inst->mayWriteToMemory()) { in isSafeToMove()
161 Stores.insert(Inst); in isSafeToMove()
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/external/llvm/lib/Target/AArch64/
DAArch64AddressTypePromotion.cpp112 bool shouldGetThrough(const Instruction *Inst);
120 bool canGetThrough(const Instruction *Inst);
157 bool AArch64AddressTypePromotion::canGetThrough(const Instruction *Inst) { in canGetThrough() argument
158 if (isa<SExtInst>(Inst)) in canGetThrough()
161 const BinaryOperator *BinOp = dyn_cast<BinaryOperator>(Inst); in canGetThrough()
167 if (isa<TruncInst>(Inst) && isa<SExtInst>(Inst->getOperand(0))) { in canGetThrough()
168 const Instruction *Opnd = cast<Instruction>(Inst->getOperand(0)); in canGetThrough()
170 if (Inst->getType()->getIntegerBitWidth() >= in canGetThrough()
172 Inst->getOperand(0)->getType()->getIntegerBitWidth() <= in canGetThrough()
180 bool AArch64AddressTypePromotion::shouldGetThrough(const Instruction *Inst) { in shouldGetThrough() argument
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/external/mesa3d/src/gallium/drivers/radeon/
DSIInstrInfo.td45 field bits<32> Inst;
51 field bits<64> Inst;
129 let Inst{3-0} = EN;
130 let Inst{9-4} = TGT;
131 let Inst{10} = COMPR;
132 let Inst{11} = DONE;
133 let Inst{12} = VM;
134 let Inst{31-26} = 0x3e;
135 let Inst{39-32} = VSRC0;
136 let Inst{47-40} = VSRC1;
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/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp141 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
143 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
146 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
149 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
151 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
153 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
155 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
157 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
159 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
161 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
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/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp33 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
36 static DecodeStatus DecodeFPR128_loRegisterClass(llvm::MCInst &Inst,
40 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
43 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
46 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
49 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
52 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
55 static DecodeStatus DecodeGPR64spRegisterClass(llvm::MCInst &Inst,
58 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
61 static DecodeStatus DecodeGPR32spRegisterClass(llvm::MCInst &Inst,
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/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp192 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
194 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
332 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
333 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
335 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
336 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
377 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
1673 void addExpr(MCInst &Inst, const MCExpr *Expr) const { in addExpr() argument
1676 Inst.addOperand(MCOperand::createImm(0)); in addExpr()
1678 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addExpr()
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/external/llvm/lib/Target/Sparc/
DSparcInstrFormats.td12 field bits<32> Inst;
18 let Inst{31-30} = op; // Top two bits are the 'op' field
39 let Inst{24-22} = op2;
40 let Inst{21-0} = imm22;
51 let Inst{29-25} = rd;
59 let Inst{29} = annul;
60 let Inst{28-25} = cond;
72 let Inst{29} = annul;
73 let Inst{28-25} = cond;
74 let Inst{24-22} = op2Val;
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/external/llvm/utils/TableGen/
DInstrInfoEmitter.cpp55 void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
71 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
88 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { in GetOperandInfo() argument
91 for (auto &Op : Inst.Operands) { in GetOperandInfo()
180 for (const CodeGenInstruction *Inst : Target.instructions()) { in EmitOperandInfo() local
181 std::vector<std::string> OperandInfo = GetOperandInfo(*Inst); in EmitOperandInfo()
207 for (const CodeGenInstruction *Inst : NumberedInstructions) { in initOperandMapData() local
208 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable")) in initOperandMapData()
211 for (const auto &Info : Inst->Operands) { in initOperandMapData()
220 OperandMap[OpList].push_back(Namespace + "::" + Inst->TheDef->getName()); in initOperandMapData()
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