Searched refs:LWZ (Results 1 – 16 of 16) sorted by relevance
| /external/llvm/test/CodeGen/MIR/PowerPC/ |
| D | unordered-implicit-registers.mir | 38 %1 = LWZ 0, %0 :: (load 4 from %ir.p)
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 68 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; in PPCRegisterInfo()
367 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) in lowerDynamicAlloc()
527 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), in lowerCRRestore()
614 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), in lowerCRBitRestore()
687 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), in lowerVRSAVERestore()
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| D | PPCAsmPrinter.cpp | 555 TmpInst.setOpcode(PPC::LWZ); in EmitInstruction()
585 TmpInst.setOpcode(PPC::LWZ); in EmitInstruction()
790 TmpInst.setOpcode(isPPC64 ? PPC::LD : PPC::LWZ); in EmitInstruction()
820 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::LWZ) in EmitInstruction()
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| D | PPCFrameLowering.cpp | 1020 : PPC::LWZ ); in emitEpilogue()
1630 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), in restoreCRs()
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| D | PPCInstrInfo.cpp | 267 case PPC::LWZ: in isLoadFromStackSlot()
1076 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), in LoadRegFromStackSlot()
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| D | PPCFastISel.cpp | 485 (Is32BitInt ? PPC::LWZ : PPC::LWZ8) : in PPCEmitLoad()
561 case PPC::LWZ: Opc = PPC::LWZX; break; in PPCEmitLoad()
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| D | PPCISelLowering.cpp | 8532 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP) in emitEHSjLjLongJmp()
8544 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp) in emitEHSjLjLongJmp()
8556 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP) in emitEHSjLjLongJmp()
8568 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP) in emitEHSjLjLongJmp()
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| D | PPCISelDAGToDAG.cpp | 4229 case PPC::LWZ: in PeepholePPC64()
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| D | PPCInstrInfo.td | 1589 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
4116 def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>;
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | no-rlwimi-trivial-commute.mir | 78 %2 = LWZ 0, %1 :: (load 4 from %ir.0)
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| /external/v8/src/ppc/ |
| D | constants-ppc.h | 122 LWZ = 32 << 26, // Load Word and Zero enumerator
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| D | assembler-ppc-inl.h | 520 const int kLoadIntptrOpcode = LWZ;
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| D | disasm-ppc.cc | 1248 case LWZ: { in InstructionDecode()
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| D | assembler-ppc.cc | 1147 d_form(LWZ, dst, src.ra(), src.offset(), true); in lwz()
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| D | simulator-ppc.cc | 3554 case LWZ: { in ExecuteGeneric()
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| /external/pcre/dist/sljit/ |
| D | sljitNativePPC_common.c | 177 #define LWZ (HI(32)) macro
568 #define STACK_LOAD LWZ
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