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/toolchain/binutils/binutils-2.25/opcodes/po/
DPOTFILES.in8 aarch64-opc-2.c
9 aarch64-opc.c
10 aarch64-opc.h
13 alpha-opc.c
16 arc-opc.c
23 cgen-opc.c
25 cr16-opc.c
27 cris-opc.c
29 crx-opc.c
31 d10v-opc.c
[all …]
Dopcodes.pot61 #: aarch64-opc.c:1152
65 #: aarch64-opc.c:1162
69 #: aarch64-opc.c:1172
73 #: aarch64-opc.c:1182
77 #: aarch64-opc.c:1192
81 #: aarch64-opc.c:1264
85 #: aarch64-opc.c:1269
89 #: aarch64-opc.c:1280
93 #: aarch64-opc.c:1310
97 #: aarch64-opc.c:1321
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/toolchain/binutils/binutils-2.25/opcodes/
DMakefile.am62 aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \
63 epiphany-desc.h epiphany-opc.h \
64 fr30-desc.h fr30-opc.h \
65 frv-desc.h frv-opc.h \
66 h8500-opc.h \
68 i386-opc.h \
71 ia64-opc.h \
72 ip2k-desc.h ip2k-opc.h \
73 iq2000-desc.h iq2000-opc.h \
75 lm32-opc.h \
[all …]
Dnds32-dis.c227 nds32_parse_opcode (struct nds32_opcode *opc, bfd_vma pc ATTRIBUTE_UNUSED, in nds32_parse_opcode() argument
242 if (opc == NULL) in nds32_parse_opcode()
251 pstr_src = opc->instruction; in nds32_parse_opcode()
254 func (stream, "%s", opc->opcode); in nds32_parse_opcode()
260 func (stream, "%s ", opc->opcode); in nds32_parse_opcode()
268 func (stream, "%s.", opc->opcode); in nds32_parse_opcode()
269 else if (strstr (opc->instruction, "tito")) in nds32_parse_opcode()
270 func (stream, "%s", opc->opcode); in nds32_parse_opcode()
272 func (stream, "%s ", opc->opcode); in nds32_parse_opcode()
315 if ((opc->value == 0xfc00) || (opc->value == 0xfc80)) in nds32_parse_opcode()
[all …]
DMakefile.in334 aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \
335 epiphany-desc.h epiphany-opc.h \
336 fr30-desc.h fr30-opc.h \
337 frv-desc.h frv-opc.h \
338 h8500-opc.h \
340 i386-opc.h \
343 ia64-opc.h \
344 ip2k-desc.h ip2k-opc.h \
345 iq2000-desc.h iq2000-opc.h \
347 lm32-opc.h \
[all …]
DChangeLog-20059 * pj-opc.c (jsr, ret, getstatic, putstatic, getfield, putfield,
28 (mt-asm.lo, mt-desc.lo, mt-dis.lo, mt-ibld.lo, mt-opc.lo): Rename &
40 * mt-opc.c: Renamed, rebuilt.
41 * mt-opc.h: Renamed, rebuilt.
46 * m32c-opc.c: Regenerate.
47 * m32c-opc.h: Regenerate.
71 * cris-opc.c (cris_opcodes) <"move" "s,P">: Define using
113 * cgen-opc.c (cgen_bitset_create, cgen_bitset_init, cgen_bitset_clear)
129 * ppc-opc.c (powerpc_opcodes): Add frin,friz,frip,frim. Correct
134 * mips16-opc.c: Add MIPS16e save/restore opcodes.
[all …]
DChangeLog-98997 * m10300-opc.c, m10300-dis.c: Add am33 support.
16 * d10v-opc.c: Fix pattern for "cpfg,f{0|1},c" instruction.
20 * mips-opc.c (I5): New.
28 * arm-opc.h (print_insn_arm): Added comment documenting
33 * mips-opc.c (la): Create a version that just uses addiu directly.
38 * mips-opc.c: Add ssnop pattern.
46 * d30v-opc.c (mvtacc): Use format SHORT_AR not SHORT_AA
59 * alpha-opc.c (alpha_operands): Fill in missing initializer.
82 * d10v-opc.c (d10v_operands): Add RESTRICTED_NUM3 flag for
91 * m32r-dis.c, m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c: Ditto.
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Dcgen.sh90 rm -f ${tmp}-opc.h ${tmp}-opc.h1
91 rm -f ${tmp}-opc.c ${tmp}-opc.c1
99 ${cgen} ${cgendir}/cgen-opc.scm \
108 -O ${tmp}-opc.h1 \
109 -P ${tmp}-opc.c1 \
123 sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" < ${tmp}-opc.h1 > ${tmp}-opc.h
124 ${rootdir}/move-if-change ${tmp}-opc.h ${srcdir}/${prefix}-opc.h
127 -e "s/@prefix@/${prefix}/" < ${tmp}-opc.c1 > ${tmp}-opc.c
128 ${rootdir}/move-if-change ${tmp}-opc.c ${srcdir}/${prefix}-opc.c
155 rm -f ${tmp}-opc.h1 ${tmp}-opc.c1
Dconfigure.ac241 cgen_files="cgen-opc.lo cgen-asm.lo cgen-dis.lo cgen-bitset.lo"
255 …ch) ta="$ta aarch64-asm.lo aarch64-dis.lo aarch64-opc.lo aarch64-asm-2.lo aarch64-dis-2.lo aarch64…
256 bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;;
257 bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
261 bfd_cr16_arch) ta="$ta cr16-dis.lo cr16-opc.lo" ;;
262 bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;;
263 bfd_crx_arch) ta="$ta crx-dis.lo crx-opc.lo" ;;
264 bfd_d10v_arch) ta="$ta d10v-dis.lo d10v-opc.lo" ;;
265 bfd_d30v_arch) ta="$ta d30v-dis.lo d30v-opc.lo" ;;
267 …bfd_fr30_arch) ta="$ta fr30-asm.lo fr30-desc.lo fr30-dis.lo fr30-ibld.lo fr30-opc.lo" using_cgen=…
[all …]
DChangeLog-20076 * i386-opc.tbl: Remove IgnoreSize from cvtsi2ss/cvtsi2sd.
18 * i386-opc.h (CpuSSE4_1_Or_5): New.
22 * i386-opc.tbl: Use CpuSSE4_1_Or_5 instead of CpuSSE4_1|CpuSSE5
30 * i386-opc.h (OldGcc): New.
37 * i386-opc.tbl: Update fadd, fdiv, fdivp, fdivr, fdivrp, fmul,
61 * mips-opc.c (IL2E): New.
70 * mips-opc.c (I3_32, I3_33, I4_32, I4_33, I5_33): New.
75 * s390-opc.txt ("tcet", "tcdt", "tcxt", "tget", "tgdt",
94 * m68k-opc.c (m68k_opcodes): Fix coldfire msac.w instructions with
109 * ppc-opc.c (powerpc_opcodes): Remove the dcffix and dcffix. opcodes
[all …]
DChangeLog-20129 * rl78-decode.opc: Likewise.
11 * rx-decode.opc: Likewise.
17 * ppc-opc.c (insert_sci8, extract_sci8): Rewrite.
23 * epiphany-desc.c, epiphany-desc.h, epiphany-opc.c: Regenerate.
31 * microblaze-opc.h: Rename INST_TYPE_RD_R1_SPECIAL to
45 * microblaze-opc.h (op_code_struct): Add swapb, swaph Increase MAX_OPCODES.
57 * i386-opc.tbl: Fix opcode for 64-bit jecxz.
62 * s390-opc.txt: Fix srstu and strag opcodes.
66 * microblaze-opc.h: Define new instruction type INST_TYPE_IMM5,
77 * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add clz insn
[all …]
DChangeLog-201330 * micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u,
34 * opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u,
55 * nds32-opc.h: New file for nds32.
65 * aarch64-opc.c (aarch64_pstatefields): Update.
69 * micromips-opc.c (LM): Define.
71 * mips-opc.c (prefe): Add LM attribute.
79 * aarch64-opc.c (CPENT): New define.
87 * aarch64-opc.c (CPENT): New define.
95 * mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
103 * mips-opc.c (LDD): Remove.
[all …]
DChangeLog-201016 * mips-opc.c (WR_z, WR_Z, RD_z, RD_Z, RD_d): Define.
22 * mips-opc.c: (mips_builtin_opcodes): Add loongson3a mul/div and
39 * mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A.
53 * mips-opc.c (mips_builtin_opcodes): Fix formatting of "ld".
57 * s390-opc.txt: cfxr, cfdr and cfer z900 -> g5.
61 * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.
74 * mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
89 * i386-opc.tbl: Remove CheckRegSize from movq.
94 * i386-opc.tbl: Remove CheckRegSize from instructions with
102 * i386-opc.h (CheckRegSize): New.
[all …]
Dxtensa-dis.c77 xtensa_opcode opc, in print_xtensa_operand() argument
93 (void) xtensa_operand_decode (isa, opc, opnd, &operand_val); in print_xtensa_operand()
96 if (xtensa_operand_is_register (isa, opc, opnd) == 0) in print_xtensa_operand()
98 if (xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) in print_xtensa_operand()
100 (void) xtensa_operand_undo_reloc (isa, opc, opnd, in print_xtensa_operand()
116 xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); in print_xtensa_operand()
120 while (i < xtensa_operand_num_regs (isa, opc, opnd)) in print_xtensa_operand()
141 xtensa_opcode opc; in print_insn_xtensa() local
234 opc = xtensa_opcode_decode (isa, fmt, n, slot_buffer); in print_insn_xtensa()
236 xtensa_opcode_name (isa, opc)); in print_insn_xtensa()
[all …]
DChangeLog-92973 * mips-opc.c: Add FP_D to s.d instruction flags.
7 * m68k-opc.c (halt, pulse): Enable them on the 68060.
11 * tic80-opc.c (tic80_opcodes): Revert change that put the 32 bit
17 * d30v-opc.c (d30v_opcode_table): Set new flags bits
31 * tic80-opc.c (OFF_SL_PC, OFF_SL_BR): Minor formatting change.
37 * alpha-opc.c (cvttq/*u*): Remove, as that suffix is invalid.
48 * d10v-opc.c (d10v_opcodes): Correct entry for RTE.
64 * arm-opc.h: Display nop pseudo ops alongside equivalent disassembly.
69 * m68k-opc.c (btst): Change Dd@s to Dd;b.
76 * m68k-opc.c: Add argument for lpstop. From Olivier Carmona
[all …]
DChangeLog-20096 * i386-opc.h (VexNDS): Removed.
16 * i386-opc.tbl: Replace VexNDS with VexVVVV=1, VexNDD with
35 * i386-opc.h (ByteOkIntel): Removed.
38 * i386-opc.tbl: Remove ByteOkIntel.
46 * i386-opc.h (Vex0F): Removed.
59 * i386-opc.tbl: Replace Vex0F with VexOpcode=0, Vex0F38 with
66 * i386-opc.h (VEX2SOURCES): Renamed to ...
74 * i386-opc.h (Vex2Sources): Removed.
82 * i386-opc.tbl: Replace Vex2Sources with VexSources=1 and
91 * i386-opc.h (VexW0): Removed.
[all …]
DChangeLog-02039 * m32r-opc.c: Regenerate.
13 * arm-opc.h (arm_opcodes): Put V6 instructions before XScale
18 * mmix-opc.c (mmix_opcodes): Use GO_INSN_BYTE, PUSHGO_INSN_BYTE,
24 * ppc-opc.c (MO): Make optional.
33 * arm-opc.h (arm_opcodes): Add V6 instructions.
39 * pj-opc.c: Update copyright date.
48 * m32r-opc.c: Regenerate.
49 * m32r-opc.h: Regenerate.
54 * sh-opc.h: Add support for sh4a and no-fpu variants.
59 * alpha-opc.c: Remove ARGSUSED.
[all …]
DChangeLog-20083 * s390-opc.txt: Add ptff instruction.
25 * lm32-opc.c: New file.
26 * lm32-opc.h: New file.
41 * i386-opc.h (S): Update comments.
43 * i386-opc.tbl: Add S to movss, movsd, vmovss and vmovsd.
80 * i386-opc.h (S): New.
84 * i386-opc.tbl: Add S to movapd, movaps, movdqa, movdqu, movq,
133 * ppc-opc.c (DE, DES, DEO, DE_MASK): Remove.
149 * ppc-opc.c (extract_sprg): Correct operand range check.
180 * mips-opc.c (synciobdma, syncs, syncw, syncws): Move these
[all …]
DChangeLog-20043 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
16 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
27 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
38 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
43 * or32-opc.c (debug): Warning fix.
69 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
100 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
145 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
152 * crx-opc.c (crx_instruction): Update data structure according to the
167 * opcodes/iq2000-opc.c: Regenerate.
[all …]
DChangeLog-00019 * ppc-opc.c (PPCVEC): Include PPC_OPCODE_ANY.
13 * alpha-opc.c (unop): Encode with RB as $sp.
27 * xstormy16-opc.c: New generated file.
28 * xstormy16-opc.h: New generated file.
32 * alpha-opc.c (alpha_opcodes): Add wh64en.
36 * d10v-opc.c (d10v_predefined_registers): Remove warnings
45 * d10v-opc.c (RSRC_NOSP): New macro.
51 * d10v-opc.c (d10v_predefined_registers): Mark `sp' as OPERAND_SP.
64 * ppc-opc.c (mfvrsave, mtvrsave): New instructions.
70 * ppc-opc.c (PPC64): Revert 2001-10-12. Do include PPC_OPCODE_PPC.
[all …]
DChangeLog-20119 * ppc-opc.c (ISA_V2): Define and use for relevant BO field tests.
20 * mips-opc.c (mips_builtin_opcodes): Add "pause".
27 * mips-opc.c (IOCT): Include Octeon2.
42 * mips-opc.c (IOCT): Include Octeon+.
57 * micromips-opc.c (micromips_opcodes): Use NODS rather than TRAP
72 (rl78-decode.c): New rule, built from rl78-decode.opc and opc2c.
79 * rl78-decode.opc: New file.
84 * ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq,
97 * epiphany-asm.c, epiphany-opc.h: Regenerate.
101 * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
[all …]
/toolchain/binutils/binutils-2.25/include/
Dxtensa-isa.h372 xtensa_insnbuf slotbuf, xtensa_opcode opc);
378 xtensa_opcode_name (xtensa_isa isa, xtensa_opcode opc);
398 xtensa_opcode_is_branch (xtensa_isa isa, xtensa_opcode opc);
401 xtensa_opcode_is_jump (xtensa_isa isa, xtensa_opcode opc);
404 xtensa_opcode_is_loop (xtensa_isa isa, xtensa_opcode opc);
407 xtensa_opcode_is_call (xtensa_isa isa, xtensa_opcode opc);
415 xtensa_opcode_num_operands (xtensa_isa isa, xtensa_opcode opc);
418 xtensa_opcode_num_stateOperands (xtensa_isa isa, xtensa_opcode opc);
421 xtensa_opcode_num_interfaceOperands (xtensa_isa isa, xtensa_opcode opc);
437 xtensa_opcode_num_funcUnit_uses (xtensa_isa isa, xtensa_opcode opc);
[all …]
/toolchain/binutils/binutils-2.25/bfd/
Dxtensa-isa.c697 xtensa_opcode opc; in xtensa_opcode_decode() local
704 opc = (intisa->slots[slot_id].opcode_decode_fn) (slotbuf); in xtensa_opcode_decode()
705 if (opc != XTENSA_UNDEFINED) in xtensa_opcode_decode()
706 return opc; in xtensa_opcode_decode()
716 xtensa_insnbuf slotbuf, xtensa_opcode opc) in xtensa_opcode_encode() argument
724 CHECK_OPCODE (intisa, opc, -1); in xtensa_opcode_encode()
727 encode_fn = intisa->opcodes[opc].encode_fns[slot_id]; in xtensa_opcode_encode()
733 intisa->opcodes[opc].name, slot, intisa->formats[fmt].name); in xtensa_opcode_encode()
742 xtensa_opcode_name (xtensa_isa isa, xtensa_opcode opc) in xtensa_opcode_name() argument
745 CHECK_OPCODE (intisa, opc, NULL); in xtensa_opcode_name()
[all …]
/toolchain/binutils/binutils-2.25/cpu/
DChangeLog7 * or1k.opc: Whitespace fixes.
24 * openrisc.opc: Delete.
26 * or1k.opc: New file.
33 * epiphany.opc: Remove +x file mode.
61 * mt.opc (print_dollarhex): Trim values to 32 bits.
65 * frv.opc (parse_uhi16): Fix handling of %hi operator on 64-bit
70 * epiphany.opc (parse_branch_addr): Fix type of valuep.
77 * cpu/epiphany.opc: New file.
82 * fr30.opc: Likewise.
84 * ip2k.opc: Likewise.
[all …]
/toolchain/binutils/binutils-2.25/gas/config/
Dtc-m68hc11.c473 struct m68hc11_opcode_def *opc; in m68hc11_print_statistics() local
477 opc = m68hc11_opcode_defs; in m68hc11_print_statistics()
478 if (opc == 0 || m68hc11_nb_opcode_defs == 0) in m68hc11_print_statistics()
483 for (i = 0; i < m68hc11_nb_opcode_defs; i++, opc++) in m68hc11_print_statistics()
486 opc->opcode->name, in m68hc11_print_statistics()
487 opc->nb_modes, in m68hc11_print_statistics()
488 opc->min_operands, opc->max_operands, opc->format, opc->used); in m68hc11_print_statistics()
608 struct m68hc11_opcode_def *opc = 0; in md_begin() local
647 opc = (struct m68hc11_opcode_def *) in md_begin()
649 m68hc11_opcode_defs = opc--; in md_begin()
[all …]

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