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Searched refs:RegVT (Results 1 – 15 of 15) sorted by relevance

/external/llvm/lib/CodeGen/
DCallingConvLower.cpp240 for (MVT RegVT : RegParmTypes) { in analyzeMustTailForwardedRegisters() local
242 getRemainingRegParmsForType(RemainingRegs, RegVT, Fn); in analyzeMustTailForwardedRegisters()
244 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
247 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT)); in analyzeMustTailForwardedRegisters()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1068 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1069 if (RegVT == MVT::i8 || RegVT == MVT::i16 || in LowerFormalArguments()
1070 RegVT == MVT::i32 || RegVT == MVT::f32) { in LowerFormalArguments()
1074 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
1075 } else if (RegVT == MVT::i64 || RegVT == MVT::f64) { in LowerFormalArguments()
1079 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
1082 } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 || in LowerFormalArguments()
1083 RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) { in LowerFormalArguments()
1087 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
1089 ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || in LowerFormalArguments()
[all …]
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp211 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
212 switch (RegVT.getSimpleVT().SimpleTy) { in LowerFormalArguments()
215 << RegVT.getSimpleVT().SimpleTy << '\n'; in LowerFormalArguments()
221 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerFormalArguments()
227 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
230 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp452 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
453 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
458 << RegVT.getSimpleVT().SimpleTy << "\n"; in LowerCCCArguments()
465 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
471 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
474 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp2017 B.RegVT = VT.getSimpleVT(); in visitBitTestHeader()
2018 B.Reg = FuncInfo.CreateReg(B.RegVT); in visitBitTestHeader()
2047 MVT VT = BB.RegVT; in visitBitTestCase()
6029 MVT RegVT = *PhysReg.second->vt_begin(); in GetRegistersForValue() local
6030 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) { in GetRegistersForValue()
6032 RegVT, OpInfo.CallOperand); in GetRegistersForValue()
6033 OpInfo.ConstraintVT = RegVT; in GetRegistersForValue()
6034 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { in GetRegistersForValue()
6039 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits()); in GetRegistersForValue()
6041 RegVT, OpInfo.CallOperand); in GetRegistersForValue()
[all …]
DSelectionDAGBuilder.h289 : First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E), in BitTestBlock()
296 MVT RegVT; member
DLegalizeDAG.cpp342 MVT RegVT = in ExpandUnalignedStore() local
347 unsigned RegBytes = RegVT.getSizeInBits() / 8; in ExpandUnalignedStore()
351 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); in ExpandUnalignedStore()
365 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, in ExpandUnalignedStore()
387 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, in ExpandUnalignedStore()
470 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); in ExpandUnalignedLoad() local
472 unsigned RegBytes = RegVT.getSizeInBits() / 8; in ExpandUnalignedLoad()
476 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in ExpandUnalignedLoad()
487 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, in ExpandUnalignedLoad()
506 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, in ExpandUnalignedLoad()
DLegalizeVectorOps.cpp660 EVT RegVT = Value.getValueType(); in ExpandStore() local
661 EVT RegSclVT = RegVT.getScalarType(); in ExpandStore()
DLegalizeIntegerTypes.cpp817 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); in PromoteIntRes_VAARG() local
823 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2), in PromoteIntRes_VAARG()
839 DAG.getConstant(i * RegVT.getSizeInBits(), dl, in PromoteIntRes_VAARG()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp3003 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
3005 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
3010 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
3016 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || in LowerFormalArguments()
3017 (RegVT == MVT::i64 && ValVT == MVT::f64) || in LowerFormalArguments()
3018 (RegVT == MVT::f64 && ValVT == MVT::i64)) in LowerFormalArguments()
3020 else if (ABI.IsO32() && RegVT == MVT::i32 && in LowerFormalArguments()
3024 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); in LowerFormalArguments()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1330 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
1331 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
1336 << RegVT.getSimpleVT().SimpleTy << "\n"; in LowerCCCArguments()
1343 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp2700 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
2702 if (RegVT == MVT::i32) in LowerFormalArguments()
2704 else if (Is64Bit && RegVT == MVT::i64) in LowerFormalArguments()
2706 else if (RegVT == MVT::f32) in LowerFormalArguments()
2708 else if (RegVT == MVT::f64) in LowerFormalArguments()
2710 else if (RegVT == MVT::f128) in LowerFormalArguments()
2712 else if (RegVT.is512BitVector()) in LowerFormalArguments()
2714 else if (RegVT.is256BitVector()) in LowerFormalArguments()
2716 else if (RegVT.is128BitVector()) in LowerFormalArguments()
2718 else if (RegVT == MVT::x86mmx) in LowerFormalArguments()
[all …]
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp1668 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT); in performUCharToFloatCombine() local
1685 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT, in performUCharToFloatCombine()
1696 if (RegVT.isVector()) in performUCharToFloatCombine()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp2432 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
2437 if (RegVT == MVT::i32) in LowerFormalArguments()
2439 else if (RegVT == MVT::i64) in LowerFormalArguments()
2441 else if (RegVT == MVT::f16) in LowerFormalArguments()
2443 else if (RegVT == MVT::f32) in LowerFormalArguments()
2445 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
2447 else if (RegVT == MVT::f128 || RegVT.is128BitVector()) in LowerFormalArguments()
2454 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
2472 assert(RegVT == Ins[i].VT && "incorrect register location selected"); in LowerFormalArguments()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp2184 EVT RegVT = VA.getLocVT(); in IsEligibleForTailCallOptimization() local
2198 if (RegVT == MVT::v2f64) { in IsEligibleForTailCallOptimization()
3134 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
3168 if (RegVT == MVT::f32) in LowerFormalArguments()
3170 else if (RegVT == MVT::f64) in LowerFormalArguments()
3172 else if (RegVT == MVT::v2f64) in LowerFormalArguments()
3174 else if (RegVT == MVT::i32) in LowerFormalArguments()
3182 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
3195 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
3200 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()