Home
last modified time | relevance | path

Searched refs:IntRegs (Results 1 – 25 of 28) sorted by relevance

12

/external/llvm/lib/Target/Hexagon/
DHexagonSelectCCInfo.td14 def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
15 IntRegs:$fval, SETEQ)),
16 (i32 (MUX_rr (i1 (CMPEQrr IntRegs:$lhs, IntRegs:$rhs)),
17 IntRegs:$tval, IntRegs:$fval))>;
19 def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
20 IntRegs:$fval, SETNE)),
21 (i32 (MUX_rr (i1 (NOT_p (CMPEQrr IntRegs:$lhs, IntRegs:$rhs))),
22 IntRegs:$tval, IntRegs:$fval))>;
24 def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
25 IntRegs:$fval, SETGT)),
[all …]
DHexagonInstrAlias.td14 (S2_storerbnewgp u16_0Imm:$addr, IntRegs:$Nt)>;
16 (S2_storerhnewgp u16_1Imm:$addr, IntRegs:$Nt)>;
18 (S2_storerinewgp u16_2Imm:$addr, IntRegs:$Nt)>;
20 (S2_storerbgp u16_0Imm:$addr, IntRegs:$Nt)>;
22 (S2_storerhgp u16_1Imm:$addr, IntRegs:$Nt)>;
24 (S2_storerfgp u16_1Imm:$addr, IntRegs:$Nt)>;
26 (S2_storerigp u16_2Imm:$addr, IntRegs:$Nt)>;
31 (L2_loadrbgp IntRegs:$Nt, u16_0Imm:$addr)>;
33 (L2_loadrubgp IntRegs:$Nt, u16_0Imm:$addr)>;
35 (L2_loadrhgp IntRegs:$Nt, u16_1Imm:$addr)>;
[all …]
DHexagonIsetDx.td82 (ins IntRegs:$Rs, u4_0Imm:$u4_0),
95 (outs IntRegs:$Rd),
108 (outs IntRegs:$Rd),
109 (ins IntRegs:$Rs, u3_1Imm:$u3_1),
134 (outs IntRegs:$Rx),
135 (ins IntRegs:$_src_, s7Ext:$s7),
150 (outs IntRegs:$Rd),
151 (ins IntRegs:$Rs, u4_0Imm:$u4_0),
166 (outs IntRegs:$Rd),
167 (ins IntRegs:$Rs, u4_2Imm:$u4_2),
[all …]
DHexagonInstrInfo.td23 def I32 : PatLeaf<(i32 IntRegs:$R)>;
25 def F32 : PatLeaf<(f32 IntRegs:$R)>;
70 (ins IntRegs:$src1, ImmOp:$src2),
97 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
98 (MI IntRegs:$src1, ImmPred:$src2)>;
121 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
144 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
229 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
230 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
257 : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
[all …]
DHexagonInstrInfoV4.td165 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
194 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
196 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
197 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
199 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>;
200 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
202 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>;
203 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
205 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>;
210 : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
[all …]
DHexagonIntrinsicsV60.td165 def : Pat <(store (v512i1 VecPredRegs:$src1), (i32 IntRegs:$addr)),
166 (V6_vS32b_ai IntRegs:$addr, 0,
171 def : Pat <(v512i1 (load (i32 IntRegs:$addr))),
173 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>,
176 def : Pat <(store (v1024i1 VecPredRegs128B:$src1), (i32 IntRegs:$addr)),
177 (V6_vS32b_ai_128B IntRegs:$addr, 0,
182 def : Pat <(v1024i1 (load (i32 IntRegs:$addr))),
184 (v32i32 (V6_vL32b_ai_128B IntRegs:$addr, 0)),
190 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>,
192 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
[all …]
DHexagonInstrInfoV3.td108 (ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)",
109 [(set (i64 DoubleRegs:$Rd), (i64 (add (i64 (sext (i32 IntRegs:$Rs))),
162 //def : Pat <(brcond (i1 (seteq (i32 IntRegs:$src1), 0)), bb:$offset),
163 // (JMP_RegEzt (i32 IntRegs:$src1), bb:$offset)>;
165 //def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), 0)), bb:$offset),
166 // (JMP_RegNzt (i32 IntRegs:$src1), bb:$offset)>;
168 //def : Pat <(brcond (i1 (setle (i32 IntRegs:$src1), 0)), bb:$offset),
169 // (JMP_RegLezt (i32 IntRegs:$src1), bb:$offset)>;
171 //def : Pat <(brcond (i1 (setge (i32 IntRegs:$src1), 0)), bb:$offset),
172 // (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>;
[all …]
DHexagonInstrInfoV60.td60 : V6_LDInst <(outs VectorRegs:$dst), (ins IntRegs:$src1, s4_6Imm:$src2),
65 : V6_LDInst <(outs VectorRegs128B:$dst), (ins IntRegs:$src1, s4_7Imm:$src2),
123 : V6_STInst <(outs), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
162 : V6_STInst <(outs ), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
193 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
255 (ins VecPredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
294 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
339 : V6_LDInst <(outs RC:$dst, IntRegs:$_dst_),
340 (ins IntRegs:$src1, ImmOp:$src2), asmStr, [],
405 : V6_STInst <(outs IntRegs:$_dst_),
[all …]
DHexagonSystemInst.td61 def Y2_dccleana: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs),
63 def Y2_dcinva: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs),
65 def Y2_dccleaninva: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs),
71 def Y4_l2fetch: ST_MISC_CACHEOP_SYS<(outs), (ins IntRegs:$Rs, IntRegs:$Rt),
73 def Y5_l2fetch: ST_MISC_CACHEOP_SYS<(outs), (ins IntRegs:$Rs, DoubleRegs:$Rt),
80 (outs), (ins IntRegs:$Rs),
95 def Y2_dczeroa: ST0Inst <(outs), (ins IntRegs:$Rs),
DHexagonInstrInfoV5.td43 def A5_vaddhubs: T_S3op_1 <"vaddhub", IntRegs, 0b01, 0b001, 0, 1>;
75 def FCONST32_nsdata : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
88 def CONST32_Float_Real : LDInst<(outs IntRegs:$dst), (ins f32imm:$src1),
102 def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32Ext:$src1),
109 def TFRI_cPt_f : ALU32_ri<(outs IntRegs:$dst),
116 def TFRI_cNotPt_f : ALU32_ri<(outs IntRegs:$dst),
127 def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
152 : MInst<(outs IntRegs:$Rd),
153 (ins IntRegs:$Rs, IntRegs:$Rt),
218 (outs IntRegs:$Rd, PredRegs:$Pe),
[all …]
DHexagonInstrInfoVector.td17 def V4I8: PatLeaf<(v4i8 IntRegs:$R)>;
18 def V2I16: PatLeaf<(v2i16 IntRegs:$R)>;
25 def : Pat <(b (bitconvert (a IntRegs:$src))),
26 (b IntRegs:$src)>;
27 def : Pat <(a (bitconvert (b IntRegs:$src))),
28 (a IntRegs:$src)>;
69 def : Pat<(v2i16 (add (v2i16 IntRegs:$src1), (v2i16 IntRegs:$src2))),
70 (A2_svaddh IntRegs:$src1, IntRegs:$src2)>;
72 def : Pat<(v2i16 (sub (v2i16 IntRegs:$src1), (v2i16 IntRegs:$src2))),
73 (A2_svsubh IntRegs:$src1, IntRegs:$src2)>;
[all …]
DHexagonIntrinsicsV4.td169 def : Pat <(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2,
171 (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2ImmPred:$src3)>;
176 IntRegs:$src3, u2ImmPred:$src4),
178 IntRegs:$src3, u2ImmPred:$src4)>;
DHexagonRegisterInfo.td212 def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32,
282 def PositiveHalfWord : PatLeaf<(i32 IntRegs:$a),
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
DSparcInstrInfo.td72 let MIOperandInfo = (ops IntRegs, IntRegs);
76 let MIOperandInfo = (ops IntRegs, i32imm);
183 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
185 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
187 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
189 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>;
196 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
199 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
258 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
260 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F,
[all …]
DSparcRegisterInfo.td142 def IntRegs : RegisterClass<"SP", [i32], 32,
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td23 (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
28 (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
48 (movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>;
52 (movri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, condVal)>;
141 (TICCrr G0, IntRegs:$rs2, condVal)>,
145 (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
151 (TXCCrr G0, IntRegs:$rs2, condVal)>,
155 (TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
161 // (TICCrr G0, IntRegs:$rs2, condVal)>,
166 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
[all …]
DSparcInstrInfo.td307 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
311 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
350 def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$dst), (ins MEMrr:$addr),
352 def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$dst), (ins MEMri:$addr),
354 def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$dst),
432 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
454 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
474 def EH_SJLJ_SETJMP32ri : Pseudo<(outs IntRegs:$dst), (ins MEMri:$buf),
478 def EH_SJLJ_SETJMP32rr : Pseudo<(outs IntRegs:$dst), (ins MEMrr:$buf),
495 defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8, IntRegs, i32>;
[all …]
DSparcInstr64Bit.td23 def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>;
197 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
208 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
217 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
244 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
317 def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd),
318 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
322 def MOVXCCri : F4_2<0b101100, (outs IntRegs:$rd),
323 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
385 (ins I64Regs:$rs1, IntRegs:$rs2),
[all …]
DSparcRegisterInfo.td328 def IntRegs : RegisterClass<"SP", [i32, i64], 32,
335 // Should be in the same order as IntRegs.
344 // to be a sub-class of IntRegs. That works out because requiring a 64-bit
346 def I64Regs : RegisterClass<"SP", [i64], 64, (add IntRegs)>;
/external/llvm/docs/
DHowToUseInstrMappings.rst121 def ADD : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$a, IntRegs:$b),
123 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$a),
124 (i32 IntRegs:$b)))]>;
126 def ADD_Pt : ALU32_rr<(outs IntRegs:$dst),
127 (ins PredRegs:$p, IntRegs:$a, IntRegs:$b),
131 def ADD_Pf : ALU32_rr<(outs IntRegs:$dst),
132 (ins PredRegs:$p, IntRegs:$a, IntRegs:$b),
142 def ADD : PredRel, ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$a, IntRegs:$b),
144 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$a),
145 (i32 IntRegs:$b)))]> {
[all …]
DWritingAnLLVMBackend.rst529 ``FPRegs``, ``DFPRegs``, and ``IntRegs``. For all three register classes, the
544 def IntRegs : RegisterClass<"SP", [i32], 32,
571 associated register classes. The order of registers in ``IntRegs`` reflects
572 the order in the definition of ``IntRegs`` in the target description file.
576 // IntRegs Register Class...
577 static const unsigned IntRegs[] = {
596 // IntRegs Sub-register Classess...
601 // IntRegs Super-register Classess...
606 // IntRegs Register Class sub-classes...
611 // IntRegs Register Class super-classes...
[all …]
/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp101 static const MCPhysReg IntRegs[32] = { variable
1047 RegNo = IntRegs[intVal]; in matchRegisterName()
1055 RegNo = IntRegs[8 + intVal]; in matchRegisterName()
1062 RegNo = IntRegs[16 + intVal]; in matchRegisterName()
1069 RegNo = IntRegs[24 + intVal]; in matchRegisterName()
1093 RegNo = IntRegs[intVal]; in matchRegisterName()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsISelLowering.cpp1729 static const unsigned IntRegs[] = { in CC_MipsO32() local
1744 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize); in CC_MipsO32()
1746 State.AllocateReg(IntRegs[r]); in CC_MipsO32()
1772 Reg = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
1776 Reg = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
1781 Reg = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
1783 Reg = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
1784 State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
1791 State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
1795 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
[all …]
/external/valgrind/none/tests/amd64/
Dgen_insn_test.pl86 our @IntRegs = (
217 my @intregs = @IntRegs;
/external/valgrind/none/tests/x86/
Dgen_insn_test.pl70 our @IntRegs = (
195 my @intregs = @IntRegs;

12