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/external/llvm/lib/Target/Mips/
DMicroMips64r6InstrFormats.td68 let Inst{7-6} = 0b00;
84 let Inst{10-9} = 0b00;
117 let Inst{10-9} = 0b00;
172 let Inst{10-9} = 0b00;
219 let Inst{10-9} = 0b00;
DMipsMSAInstrInfo.td397 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
402 class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>;
407 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
412 class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>;
417 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
422 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
429 class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>;
431 class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
436 class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>;
441 class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
[all …]
DMipsMSAInstrFormats.td201 let Inst{21-20} = 0b00;
253 let Inst{21-20} = 0b00;
305 let Inst{21-20} = 0b00;
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td1111 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd),
1118 : NLdSt<0,0b00,0b1010,op7_4, (outs),
1143 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
1150 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
1175 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1183 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
1207 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1216 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
1240 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1248 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
[all …]
DARMInstrThumb2.td514 let Inst{7-6} = 0b00; // imm2
515 let Inst{5-4} = 0b00; // type
592 let Inst{7-6} = 0b00; // imm2
593 let Inst{5-4} = 0b00; // type
681 let Inst{7-6} = 0b00; // imm2
682 let Inst{5-4} = 0b00; // type
722 let Inst{7-6} = 0b00; // imm2
723 let Inst{5-4} = 0b00; // type
845 let Inst{7-6} = 0b00; // imm2
846 let Inst{5-4} = 0b00; // type
[all …]
DARMInstrVFP.td85 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
89 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
228 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
233 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
477 let Inst{6-5} = 0b00;
498 let Inst{6-5} = 0b00;
522 let Inst{7-6} = 0b00;
543 let Inst{7-6} = 0b00;
570 let Inst{7-6} = 0b00;
593 let Inst{7-6} = 0b00;
[all …]
/external/skia/src/core/
DSkMatrix44.cpp454 double b00 = a00 * a11 - a01 * a10; in determinant() local
468 return b00 * b11 - b01 * b10 + b02 * b09 + b03 * b08 - b04 * b07 + b05 * b06; in determinant()
569 double b00 = a00 * a11 - a01 * a10; in invert() local
580 double det = b00 * b11 - b01 * b10 + b03 * b08; in invert()
590 b00 *= invdet; in invert()
610 inverse->fMat[2][2] = SkDoubleToMScalar(b00); in invert()
614 inverse->fMat[3][2] = SkDoubleToMScalar(a31 * b01 - a30 * b03 - a32 * b00); in invert()
627 double b00 = a00 * a11 - a01 * a10; in invert() local
641 double det = b00 * b11 - b01 * b10 + b02 * b09 + b03 * b08 - b04 * b07 + b05 * b06; in invert()
651 b00 *= invdet; in invert()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td961 let Inst{20-19} = 0b00;
989 let Inst{20-19} = 0b00;
1373 let Inst{15-14} = 0b00;
2236 let Inst{11-10} = 0b00;
2474 let Inst{25-24} = 0b00;
2489 let Inst{25-24} = 0b00;
2586 let Inst{25-24} = 0b00;
2664 let Inst{25-24} = 0b00;
2736 let Inst{25-24} = 0b00;
2808 let Inst{25-24} = 0b00;
[all …]
DAArch64InstrInfo.td443 defm MOVN : MoveImmediate<0b00, "movn">;
703 defm LSLV : Shift<0b00, "lsl", shl>;
801 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
806 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
886 defm AND : LogicalImm<0b00, "and", and, "bic">;
903 defm AND : LogicalReg<0b00, 0, "and", and>;
904 defm BIC : LogicalReg<0b00, 1, "bic",
1005 defm SBFM : BitfieldImm<0b00, "sbfm">;
1112 defm CSEL : CondSelect<0, 0b00, "csel">;
1116 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
[all …]
/external/protobuf/src/google/protobuf/stubs/
Dint128.h343 uint64 b00 = b.lo_ & 0xffffffffu; variable
347 uint64 c96 = a96 * b00 + a64 * b32 + a32 * b64 + a00 * b96;
348 uint64 c64 = a64 * b00 + a32 * b32 + a00 * b64;
352 *this += uint128(a32 * b00) << 32;
354 *this += a00 * b00;
/external/eigen/Eigen/src/SparseLU/
DSparseLU_gemm_kernel.h74 Packet b00, b10, b20, b30, b01, b11, b21, b31; in sparselu_gemm() local
75 { b00 = pset1<Packet>(Bc0[0]); } in sparselu_gemm()
111 KMADD(c0, a0, b00, t0) \ in sparselu_gemm()
178 Packet b00, b10, b20, b30; in sparselu_gemm() local
179 b00 = pset1<Packet>(Bc0[0]); in sparselu_gemm()
208 KMADD(c0, a0, b00, t0) \ in sparselu_gemm()
/external/clang/test/CodeGenCXX/
Dbitfield.cpp13 unsigned b00 : 14; member
35 return s->b00; in read00()
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td88 let Inst{3-2} = 0b00;
92 def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>;
272 let Inst{3-2} = 0b00;
277 def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>;
455 def A2_andir : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
499 let Inst{27-26} = 0b00;
1069 def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>;
1073 def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>;
1078 def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>;
1082 def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>;
[all …]
DHexagonSystemInst.td87 let Inst{13-12} = 0b00;
131 def J2_trap0 : J2_MISC_TRAP_PAUSE<"trap0", 0b00>;
DHexagonInstrInfoV4.td144 def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>;
237 def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8Imm, 0, 0, 8>;
240 def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8Ext, 1, 1, 8>;
311 def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
581 let Inst{27-26} = 0b00;
750 def S4_storerbnew_ap : T_ST_absset_nv <"memb", "STrib", 0b00, ByteAccess>;
837 let Inst{12-11} = 0b00;
847 def S4_storerbnew_ur : T_StoreAbsRegNV <"memb", "STrib", 0b00, ByteAccess>;
1021 ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
1155 defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>;
[all …]
DHexagonInstrEnc.td308 let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, opc{2-0}, dst{4-0} };
327 let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, opc{2-0}, dst{4-0} };
346 let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, opc{2-0}, src3{4-0} };
357 let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, opc{2-0}, src3{4-0} };
376 let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, 0b00100, src3{2-0} };
390 let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, 0b00100, src3{2-0} };
841 let Inst{31-16} = { opc{8-7}, 0, opc{6-3}, 0b00, opc{2-1}, src2{4-0} };
963 let Inst{13-0} = { 0b00, opc{2}, 0b0000, opc{1-0}, 0b00000 };
DHexagonInstrInfoVector.td165 def S2_asr_r_vw : T_S3op_shiftVect < "vasrw", 0b00, 0b00>;
166 def S2_lsr_r_vw : T_S3op_shiftVect < "vlsrw", 0b00, 0b01>;
167 def S2_asl_r_vw : T_S3op_shiftVect < "vaslw", 0b00, 0b10>;
168 def S2_lsl_r_vw : T_S3op_shiftVect < "vlslw", 0b00, 0b11>;
171 def S2_asr_r_vh : T_S3op_shiftVect < "vasrh", 0b01, 0b00>;
DHexagonIsetDx.td142 let Inst{12-11} = 0b00;
242 let Inst{12-11} = 0b00;
312 let Inst{12-11} = 0b00;
372 let Inst{4-3} = 0b00;
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td1651 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd),
1658 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd),
1677 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1685 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1695 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1703 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1725 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1733 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1741 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1767 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
[all …]
DARMInstrThumb2.td602 let Inst{7-6} = 0b00; // imm2
603 let Inst{5-4} = 0b00; // type
686 let Inst{7-6} = 0b00; // imm2
687 let Inst{5-4} = 0b00; // type
807 let Inst{7-6} = 0b00; // imm2
808 let Inst{5-4} = 0b00; // type
849 let Inst{7-6} = 0b00; // imm2
850 let Inst{5-4} = 0b00; // type
947 let Inst{7-6} = 0b00; // imm2
948 let Inst{5-4} = 0b00; // type
[all …]
DARMInstrVFP.td120 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
124 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
132 def VSTRH : AHI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5fp16:$addr),
233 let Inst{24-23} = 0b00;
246 let Inst{24-23} = 0b00;
380 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
386 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
392 def VDIVH : AHbI<0b11101, 0b00, 0, 0,
464 defm VSELEQ : vsel_inst<"eq", 0b00, 0>;
469 def H : AHbInp<0b11101, 0b00, opc,
[all …]
/external/llvm/test/TableGen/
DBitsInit.td32 bits<2> D2 = { 0b00 }; // ok
34 bits<3> D4 = { 0b00 }; // type mismatch. RHS doesn't have enough bits
/external/llvm/test/DebugInfo/SystemZ/
Deh_frame_personality.s65 # CHECK-NEXT: 0010 0e079b00 0000001b 1b0c0fa0 01000000 ................
/external/tcpdump/tests/
Dkday8.out14 0x0020: d706 0b00 3c00 0000 3c00 0000 0080 0000
Dkday2.out14 0x0020: d706 0b00 3c00 0000 3c00 0000 0080 0000

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