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/external/vixl/src/aarch32/
Dassembler-aarch32.h247 Register rn,
256 Register rn,
270 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width);
275 typedef void (Assembler::*InstructionRL)(Register rn, Location* location);
282 Register rn,
286 Register rn,
291 Register rn,
303 Register rn,
307 Register rn,
322 Condition cond, Register rd, Register rn, Register rm, Register ra);
[all …]
Dmacro-assembler-aarch32.h865 Register rn,
872 Register rn,
880 Register rn,
893 Register rn,
901 Register rn,
906 Register rn,
989 void Adc(Condition cond, Register rd, Register rn, const Operand& operand) { in Adc() argument
991 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); in Adc()
998 operand.IsPlainRegister() && rn.IsLow() && rd.Is(rn) && in Adc()
1001 adc(cond, rd, rn, operand); in Adc()
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Dassembler-aarch32.cc1911 Register rn, in adc() argument
1921 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in adc()
1922 EmitT32_32(0xf1400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in adc()
1934 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in adc()
1945 if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() && in adc()
1958 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in adc()
1960 EmitT32_32(0xeb400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in adc()
1971 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in adc()
1984 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in adc()
1987 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in adc()
[all …]
Ddisasm-aarch32.h612 Register rn,
618 Register rn,
624 Register rn,
632 Register rn,
637 void addw(Condition cond, Register rd, Register rn, const Operand& operand);
644 Register rn,
650 Register rn,
670 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width);
675 Register rn,
681 Register rn,
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Ddisasm-aarch32.cc1119 Register rn, in adc() argument
1124 if (!rd.Is(rn) || !use_short_hand_form_) { in adc()
1127 os() << rn << ", " << operand; in adc()
1133 Register rn, in adcs() argument
1138 if (!rd.Is(rn) || !use_short_hand_form_) { in adcs()
1141 os() << rn << ", " << operand; in adcs()
1147 Register rn, in add() argument
1152 if (!rd.Is(rn) || !use_short_hand_form_) { in add()
1155 os() << rn << ", " << operand; in add()
1167 Register rn, in adds() argument
[all …]
Dmacro-assembler-aarch32.cc665 Register rn, in Delegate() argument
681 teq(cond, rn, scratch); in Delegate()
684 Assembler::Delegate(type, instruction, cond, rn, operand); in Delegate()
692 Register rn, in Delegate() argument
731 (this->*instruction)(cond, size, rn, scratch); in Delegate()
740 if (!rn.IsPC()) { in Delegate()
742 HandleOutOfBoundsImmediate(cond, rn, imm); in Delegate()
745 tst(cond, rn, rn); in Delegate()
762 if (IsUsingA32() || !rn.IsPC()) { in Delegate()
767 (this->*instruction)(cond, size, rn, scratch); in Delegate()
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/external/valgrind/none/tests/arm/
Dv6media.stdout.exp2 mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[…
3 mul r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[…
4 mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[…
5 mul r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[…
6 mul r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000 ge[…
7 mul r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x00000000 ge[…
9 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x…
10 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x…
11 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x…
12 mla r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x…
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Dv6intARM.stdout.exp25 adds r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000 Z
26 adds r0, r1, r2 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, carryin 0, cpsr 0x00000000
27 adds r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 0, cpsr 0x00000000
28 adds r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 0, cpsr 0x00000000
29 adds r0, r1, r2 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x80000000 N
30 adds r0, r1, r2 :: rd 0x00000000 rm 0x00000001, rn 0xffffffff, carryin 0, cpsr 0x60000000 ZC
31 adds r0, r1, r2 :: rd 0x80000000 rm 0x7fffffff, rn 0x00000001, carryin 0, cpsr 0x90000000 N V
32 adds r0, r1, r2 :: rd 0x7fffffff rm 0x80000000, rn 0xffffffff, carryin 0, cpsr 0x30000000 CV
33 adds r0, r1, r2 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, carryin 0, cpsr 0x80000000 N
35 adcs r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000 Z
[all …]
/external/valgrind/none/tests/arm64/
Dcrc32.stdout.exp2 crc32b w21,w20,w19 :: rd 00000000f8957d4c rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 000…
3 crc32b w21,w20,w19 :: rd 00000000f810b326 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 000…
4 crc32b w21,w20,w19 :: rd 00000000ef405c96 rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 000…
5 crc32b w21,w20,w19 :: rd 00000000a0db523c rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 000…
6 crc32b w21,w20,w19 :: rd 0000000096de687b rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 000…
7 crc32b w21,w20,w19 :: rd 000000005b546bd0 rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 000…
8 crc32b w21,w20,w19 :: rd 000000008f7a8684 rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 000…
9 crc32h w21,w20,w19 :: rd 00000000862b47a9 rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 000…
10 crc32h w21,w20,w19 :: rd 000000009a47a305 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 000…
11 crc32h w21,w20,w19 :: rd 00000000a788663d rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 000…
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Dinteger.stdout.exp2 add x3, x4, x5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 0000000…
3 add w3, w4, w5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 0000000…
4 adc x3, x4, x5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 0000000…
5 adc x3, x4, x5 :: rd 0000000000004abf rm 0000000000003039, rn 0000000000001a85, cin 1, nzcv 2000000…
6 adc x3, x4, x5 :: rd ffffffffffffffff rm 0000000000000000, rn ffffffffffffffff, cin 0, nzcv 0000000…
7 adc x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn ffffffffffffffff, cin 1, nzcv 2000000…
8 adc x3, x4, x5 :: rd 5859704f00000000 rm 3141592700000000, rn 2718172800000000, cin 0, nzcv 0000000…
9 adc x3, x4, x5 :: rd 5859704f00000001 rm 3141592700000000, rn 2718172800000000, cin 1, nzcv 2000000…
10 adc x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn 0000000000000000, cin 0, nzcv 0000000…
11 adc x3, x4, x5 :: rd 0000000000000001 rm 0000000000000000, rn 0000000000000000, cin 1, nzcv 2000000…
[all …]
/external/v8/src/arm64/
Dmacro-assembler-arm64-inl.h47 const Register& rn, in And() argument
51 LogicalMacro(rd, rn, operand, AND); in And()
56 const Register& rn, in Ands() argument
60 LogicalMacro(rd, rn, operand, ANDS); in Ands()
64 void MacroAssembler::Tst(const Register& rn, in Tst() argument
67 LogicalMacro(AppropriateZeroRegFor(rn), rn, operand, ANDS); in Tst()
72 const Register& rn, in Bic() argument
76 LogicalMacro(rd, rn, operand, BIC); in Bic()
81 const Register& rn, in Bics() argument
85 LogicalMacro(rd, rn, operand, BICS); in Bics()
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Dassembler-arm64.cc1094 const Register& rn, in add() argument
1096 AddSub(rd, rn, operand, LeaveFlags, ADD); in add()
1101 const Register& rn, in adds() argument
1103 AddSub(rd, rn, operand, SetFlags, ADD); in adds()
1107 void Assembler::cmn(const Register& rn, in cmn() argument
1109 Register zr = AppropriateZeroRegFor(rn); in cmn()
1110 adds(zr, rn, operand); in cmn()
1115 const Register& rn, in sub() argument
1117 AddSub(rd, rn, operand, LeaveFlags, SUB); in sub()
1122 const Register& rn, in subs() argument
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Dassembler-arm64.h1019 const Register& rn,
1024 const Register& rn,
1028 void cmn(const Register& rn, const Operand& operand);
1032 const Register& rn,
1037 const Register& rn,
1041 void cmp(const Register& rn, const Operand& operand);
1053 const Register& rn,
1058 const Register& rn,
1063 const Register& rn,
1068 const Register& rn,
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Dmacro-assembler-arm64.h175 const Register& rn,
178 const Register& rn,
181 const Register& rn,
184 const Register& rn,
187 const Register& rn,
190 const Register& rn,
193 const Register& rn,
196 const Register& rn,
198 inline void Tst(const Register& rn, const Operand& operand);
200 const Register& rn,
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/external/vixl/src/aarch64/
Dsimulator-aarch64.cc1555 unsigned rn = instr->GetRn(); in VisitLoadStoreExclusive() local
1567 uint64_t address = ReadRegister<uint64_t>(rn, Reg31IsStackPointer); in VisitLoadStoreExclusive()
1578 if ((rn == 31) && (AlignDown(address, 16) != address)) { in VisitLoadStoreExclusive()
1944 int32_t rn = ReadWRegister(instr->GetRn()); in VisitDataProcessing2Source() local
1946 if ((rn == kWMinInt) && (rm == -1)) { in VisitDataProcessing2Source()
1952 result = rn / rm; in VisitDataProcessing2Source()
1957 int64_t rn = ReadXRegister(instr->GetRn()); in VisitDataProcessing2Source() local
1959 if ((rn == kXMinInt) && (rm == -1)) { in VisitDataProcessing2Source()
1965 result = rn / rm; in VisitDataProcessing2Source()
1970 uint32_t rn = static_cast<uint32_t>(ReadWRegister(instr->GetRn())); in VisitDataProcessing2Source() local
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Dmacro-assembler-aarch64.h648 void And(const Register& rd, const Register& rn, const Operand& operand);
649 void Ands(const Register& rd, const Register& rn, const Operand& operand);
650 void Bic(const Register& rd, const Register& rn, const Operand& operand);
651 void Bics(const Register& rd, const Register& rn, const Operand& operand);
652 void Orr(const Register& rd, const Register& rn, const Operand& operand);
653 void Orn(const Register& rd, const Register& rn, const Operand& operand);
654 void Eor(const Register& rd, const Register& rn, const Operand& operand);
655 void Eon(const Register& rd, const Register& rn, const Operand& operand);
656 void Tst(const Register& rn, const Operand& operand);
658 const Register& rn,
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Dassembler-aarch64.h602 void add(const Register& rd, const Register& rn, const Operand& operand);
605 void adds(const Register& rd, const Register& rn, const Operand& operand);
608 void cmn(const Register& rn, const Operand& operand);
611 void sub(const Register& rd, const Register& rn, const Operand& operand);
614 void subs(const Register& rd, const Register& rn, const Operand& operand);
617 void cmp(const Register& rn, const Operand& operand);
626 void adc(const Register& rd, const Register& rn, const Operand& operand);
629 void adcs(const Register& rd, const Register& rn, const Operand& operand);
632 void sbc(const Register& rd, const Register& rn, const Operand& operand);
635 void sbcs(const Register& rd, const Register& rn, const Operand& operand);
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Dmacro-assembler-aarch64.cc731 const Register& rn, in And() argument
734 LogicalMacro(rd, rn, operand, AND); in And()
739 const Register& rn, in Ands() argument
742 LogicalMacro(rd, rn, operand, ANDS); in Ands()
746 void MacroAssembler::Tst(const Register& rn, const Operand& operand) { in Tst() argument
748 Ands(AppropriateZeroRegFor(rn), rn, operand); in Tst()
753 const Register& rn, in Bic() argument
756 LogicalMacro(rd, rn, operand, BIC); in Bic()
761 const Register& rn, in Bics() argument
764 LogicalMacro(rd, rn, operand, BICS); in Bics()
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Dassembler-aarch64.cc401 const Register& rn, in add() argument
403 AddSub(rd, rn, operand, LeaveFlags, ADD); in add()
408 const Register& rn, in adds() argument
410 AddSub(rd, rn, operand, SetFlags, ADD); in adds()
414 void Assembler::cmn(const Register& rn, const Operand& operand) { in cmn() argument
415 Register zr = AppropriateZeroRegFor(rn); in cmn()
416 adds(zr, rn, operand); in cmn()
421 const Register& rn, in sub() argument
423 AddSub(rd, rn, operand, LeaveFlags, SUB); in sub()
428 const Register& rn, in subs() argument
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/external/vixl/test/aarch32/
Dtest-simulator-rd-rn-rm-a32.cc137 Register rn; member
144 uint32_t rn; member
467 typedef void (MacroAssembler::*Fn)(Register rd, Register rn, Register rm);
503 Register rn = kTests[i].operands.rn; in TestHelper() local
506 scratch_registers.Exclude(rn); in TestHelper()
522 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn))); in TestHelper()
525 (masm.*instruction)(rd, rn, rm); in TestHelper()
528 __ Str(rn, MemOperand(result_ptr, offsetof(Inputs, rn))); in TestHelper()
553 printf("0x%08" PRIx32, results[i]->outputs[j].rn); in TestHelper()
577 uint32_t rn = results[i]->outputs[j].rn; in TestHelper() local
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Dtest-simulator-rd-rn-rm-t32.cc137 Register rn; member
144 uint32_t rn; member
467 typedef void (MacroAssembler::*Fn)(Register rd, Register rn, Register rm);
503 Register rn = kTests[i].operands.rn; in TestHelper() local
506 scratch_registers.Exclude(rn); in TestHelper()
522 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn))); in TestHelper()
525 (masm.*instruction)(rd, rn, rm); in TestHelper()
528 __ Str(rn, MemOperand(result_ptr, offsetof(Inputs, rn))); in TestHelper()
553 printf("0x%08" PRIx32, results[i]->outputs[j].rn); in TestHelper()
577 uint32_t rn = results[i]->outputs[j].rn; in TestHelper() local
[all …]
Dtest-simulator-cond-rd-rn-operand-imm12-t32.cc134 Register rn; member
141 uint32_t rn; member
899 Register rn,
937 Register rn = kTests[i].operands.rn; in TestHelper() local
941 scratch_registers.Exclude(rn); in TestHelper()
956 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn))); in TestHelper()
958 (masm.*instruction)(cond, rd, rn, op); in TestHelper()
961 __ Str(rn, MemOperand(result_ptr, offsetof(Inputs, rn))); in TestHelper()
985 printf("0x%08" PRIx32, results[i]->outputs[j].rn); in TestHelper()
1007 uint32_t rn = results[i]->outputs[j].rn; in TestHelper() local
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/external/swiftshader/third_party/subzero/src/DartARM32/
Dassembler_arm.h285 explicit Address(Register rn, int32_t offset = 0, Mode am = Offset) {
293 encoding_ |= static_cast<uint32_t>(rn) << kRnShift;
299 Address(Register rn, Register r, Mode am);
301 Address(Register rn, Register rm,
310 encoding_ = o.encoding() | am | (static_cast<uint32_t>(rn) << kRnShift);
314 Address(Register rn, Register rm, Shift shift, Register r, Mode am = Offset);
329 Register rn() const { in rn() function
450 void and_(Register rd, Register rn, Operand o, Condition cond = AL);
453 void eor(Register rd, Register rn, Operand o, Condition cond = AL);
456 void sub(Register rd, Register rn, Operand o, Condition cond = AL);
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/external/llvm/test/CodeGen/NVPTX/
Dconvert-fp.ll49 ; CHECK: cvt.rn.f32.u16 %f{{[0-9]+}}, %rs{{[0-9]+}};
56 ; CHECK: cvt.rn.f32.u32 %f{{[0-9]+}}, %r{{[0-9]+}};
63 ; CHECK: cvt.rn.f32.u64 %f{{[0-9]+}}, %rd{{[0-9]+}};
70 ; CHECK: cvt.rn.f32.f64 %f{{[0-9]+}}, %fd{{[0-9]+}};
77 ; CHECK: cvt.rn.f32.s16 %f{{[0-9]+}}, %rs{{[0-9]+}}
84 ; CHECK: cvt.rn.f32.s32 %f{{[0-9]+}}, %r{{[0-9]+}}
91 ; CHECK: cvt.rn.f32.s64 %f{{[0-9]+}}, %rd{{[0-9]+}}
98 ; CHECK: cvt.rn.f64.u16 %fd{{[0-9]+}}, %rs{{[0-9]+}};
105 ; CHECK: cvt.rn.f64.u32 %fd{{[0-9]+}}, %r{{[0-9]+}};
112 ; CHECK: cvt.rn.f64.u64 %fd{{[0-9]+}}, %rd{{[0-9]+}};
[all …]
/external/syslinux/core/lwip/src/core/snmp/
Dmib_structs.c216 snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn) in snmp_mib_node_insert() argument
221 LWIP_ASSERT("rn != NULL",rn != NULL); in snmp_mib_node_insert()
225 if (rn->head == NULL) in snmp_mib_node_insert()
232 rn->head = nn; in snmp_mib_node_insert()
233 rn->tail = nn; in snmp_mib_node_insert()
246 n = rn->head; in snmp_mib_node_insert()
268 rn->tail = nn; in snmp_mib_node_insert()
298 rn->head = nn; in snmp_mib_node_insert()
322 rn->count += 1; in snmp_mib_node_insert()
338 snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn) in snmp_mib_node_find() argument
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