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Searched refs:ARM_AM (Results 1 – 25 of 72) sorted by relevance

123

/external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp65 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); in printInst()
73 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); in printInst()
84 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
91 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
96 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); in printInst()
249 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand()
250 O << ", " << ARM_AM::getShiftOpcStr(ShOpc); in printSORegRegOperand()
251 if (ShOpc == ARM_AM::rrx) in printSORegRegOperand()
255 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); in printSORegRegOperand()
266 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm()); in printSORegImmOperand()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp132 static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) { in getLoadStoreMultipleOpcode()
139 case ARM_AM::ia: return ARM::LDMIA; in getLoadStoreMultipleOpcode()
140 case ARM_AM::da: return ARM::LDMDA; in getLoadStoreMultipleOpcode()
141 case ARM_AM::db: return ARM::LDMDB; in getLoadStoreMultipleOpcode()
142 case ARM_AM::ib: return ARM::LDMIB; in getLoadStoreMultipleOpcode()
149 case ARM_AM::ia: return ARM::STMIA; in getLoadStoreMultipleOpcode()
150 case ARM_AM::da: return ARM::STMDA; in getLoadStoreMultipleOpcode()
151 case ARM_AM::db: return ARM::STMDB; in getLoadStoreMultipleOpcode()
152 case ARM_AM::ib: return ARM::STMIB; in getLoadStoreMultipleOpcode()
160 case ARM_AM::ia: return ARM::t2LDMIA; in getLoadStoreMultipleOpcode()
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DARMSelectionDAGInfo.h22 namespace ARM_AM {
25 default: return ARM_AM::no_shift; in getShiftOpcForNode()
26 case ISD::SHL: return ARM_AM::lsl; in getShiftOpcForNode()
27 case ISD::SRL: return ARM_AM::lsr; in getShiftOpcForNode()
28 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
29 case ISD::ROTR: return ARM_AM::ror; in getShiftOpcForNode()
DARMISelDAGToDAG.cpp97 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
184 return ARM_AM::getSOImmVal(Imm) != -1; in is_so_imm()
188 return ARM_AM::getSOImmVal(~Imm) != -1; in is_so_imm_not()
192 return ARM_AM::getT2SOImmVal(Imm) != -1; in is_t2_so_imm()
196 return ARM_AM::getT2SOImmVal(~Imm) != -1; in is_t2_so_imm_not()
380 ARM_AM::ShiftOpc ShOpcVal, in isShifterOpProfitable()
387 return ShOpcVal == ARM_AM::lsl && ShAmt == 2; in isShifterOpProfitable()
397 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectImmShifterOperand()
401 if (ShOpcVal == ARM_AM::no_shift) return false; in SelectImmShifterOperand()
408 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal), in SelectImmShifterOperand()
[all …]
DARMCodeEmitter.cpp401 switch (ARM_AM::getAM2ShiftOpc(Imm)) { in getShiftOp()
403 case ARM_AM::asr: return 2; in getShiftOp()
404 case ARM_AM::lsl: return 0; in getShiftOp()
405 case ARM_AM::lsr: return 1; in getShiftOp()
406 case ARM_AM::ror: in getShiftOp()
407 case ARM_AM::rrx: return 3; in getShiftOp()
723 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) && in emitMOVi2piecesInstruction()
725 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm()); in emitMOVi2piecesInstruction()
726 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm()); in emitMOVi2piecesInstruction()
927 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getMachineSoRegOpValue()
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DThumb2InstrInfo.cpp186 ARM_AM::getT2SOImmVal(NumBytes) == -1) { in emitT2RegPlusImmediate()
246 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) { in emitT2RegPlusImmediate()
251 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt); in emitT2RegPlusImmediate()
253 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 && in emitT2RegPlusImmediate()
259 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) { in emitT2RegPlusImmediate()
268 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt); in emitT2RegPlusImmediate()
270 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 && in emitT2RegPlusImmediate()
424 if (ARM_AM::getT2SOImmVal(Offset) != -1) { in rewriteT2FrameIndex()
450 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt); in rewriteT2FrameIndex()
455 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 && in rewriteT2FrameIndex()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp167 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); in getLdStmModeOpValue()
170 case ARM_AM::da: return 0; in getLdStmModeOpValue()
171 case ARM_AM::ia: return 1; in getLdStmModeOpValue()
172 case ARM_AM::db: return 2; in getLdStmModeOpValue()
173 case ARM_AM::ib: return 3; in getLdStmModeOpValue()
178 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp()
181 case ARM_AM::no_shift: in getShiftOp()
182 case ARM_AM::lsl: return 0; in getShiftOp()
183 case ARM_AM::lsr: return 1; in getShiftOp()
184 case ARM_AM::asr: return 2; in getShiftOp()
[all …]
DARMAddressingModes.h25 namespace ARM_AM {
47 case ARM_AM::asr: return "asr"; in getShiftOpcStr()
48 case ARM_AM::lsl: return "lsl"; in getShiftOpcStr()
49 case ARM_AM::lsr: return "lsr"; in getShiftOpcStr()
50 case ARM_AM::ror: return "ror"; in getShiftOpcStr()
51 case ARM_AM::rrx: return "rrx"; in getShiftOpcStr()
58 case ARM_AM::asr: return 2; in getShiftOpcEncoding()
59 case ARM_AM::lsl: return 0; in getShiftOpcEncoding()
60 case ARM_AM::lsr: return 1; in getShiftOpcEncoding()
61 case ARM_AM::ror: return 3; in getShiftOpcEncoding()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp207 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); in getLdStmModeOpValue()
210 case ARM_AM::da: return 0; in getLdStmModeOpValue()
211 case ARM_AM::ia: return 1; in getLdStmModeOpValue()
212 case ARM_AM::db: return 2; in getLdStmModeOpValue()
213 case ARM_AM::ib: return 3; in getLdStmModeOpValue()
219 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp()
221 case ARM_AM::no_shift: in getShiftOp()
222 case ARM_AM::lsl: return 0; in getShiftOp()
223 case ARM_AM::lsr: return 1; in getShiftOp()
224 case ARM_AM::asr: return 2; in getShiftOp()
[all …]
DARMAddressingModes.h26 namespace ARM_AM {
46 case ARM_AM::asr: return "asr"; in getShiftOpcStr()
47 case ARM_AM::lsl: return "lsl"; in getShiftOpcStr()
48 case ARM_AM::lsr: return "lsr"; in getShiftOpcStr()
49 case ARM_AM::ror: return "ror"; in getShiftOpcStr()
50 case ARM_AM::rrx: return "rrx"; in getShiftOpcStr()
57 case ARM_AM::asr: return 2; in getShiftOpcEncoding()
58 case ARM_AM::lsl: return 0; in getShiftOpcEncoding()
59 case ARM_AM::lsr: return 1; in getShiftOpcEncoding()
60 case ARM_AM::ror: return 3; in getShiftOpcEncoding()
[all …]
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp194 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); in getLdStmModeOpValue()
197 case ARM_AM::da: return 0; in getLdStmModeOpValue()
198 case ARM_AM::ia: return 1; in getLdStmModeOpValue()
199 case ARM_AM::db: return 2; in getLdStmModeOpValue()
200 case ARM_AM::ib: return 3; in getLdStmModeOpValue()
205 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp()
207 case ARM_AM::no_shift: in getShiftOp()
208 case ARM_AM::lsl: return 0; in getShiftOp()
209 case ARM_AM::lsr: return 1; in getShiftOp()
210 case ARM_AM::asr: return 2; in getShiftOp()
[all …]
DARMAddressingModes.h26 namespace ARM_AM {
48 case ARM_AM::asr: return "asr"; in getShiftOpcStr()
49 case ARM_AM::lsl: return "lsl"; in getShiftOpcStr()
50 case ARM_AM::lsr: return "lsr"; in getShiftOpcStr()
51 case ARM_AM::ror: return "ror"; in getShiftOpcStr()
52 case ARM_AM::rrx: return "rrx"; in getShiftOpcStr()
59 case ARM_AM::asr: return 2; in getShiftOpcEncoding()
60 case ARM_AM::lsl: return 0; in getShiftOpcEncoding()
61 case ARM_AM::lsr: return 1; in getShiftOpcEncoding()
62 case ARM_AM::ror: return 3; in getShiftOpcEncoding()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp53 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, in printRegImmShift()
55 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) in printRegImmShift()
59 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0"); in printRegImmShift()
62 if (ShOpc != ARM_AM::rrx) { in printRegImmShift()
93 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); in printInst()
104 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); in printInst()
115 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
124 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
130 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">"); in printInst()
364 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand()
[all …]
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp44 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, in printRegImmShift()
46 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) in printRegImmShift()
50 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0"); in printRegImmShift()
53 if (ShOpc != ARM_AM::rrx) { in printRegImmShift()
85 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); in printInst()
96 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); in printInst()
107 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
116 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
122 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">"); in printInst()
352 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp232 int Offset = isAM3 ? ARM_AM::getAM3Offset(OffField) in getMemoryOpOffset()
233 : ARM_AM::getAM5Offset(OffField) * 4; in getMemoryOpOffset()
234 ARM_AM::AddrOpc Op = isAM3 ? ARM_AM::getAM3Op(OffField) in getMemoryOpOffset()
235 : ARM_AM::getAM5Op(OffField); in getMemoryOpOffset()
237 if (Op == ARM_AM::sub) in getMemoryOpOffset()
251 static int getLoadStoreMultipleOpcode(unsigned Opcode, ARM_AM::AMSubMode Mode) { in getLoadStoreMultipleOpcode()
258 case ARM_AM::ia: return ARM::LDMIA; in getLoadStoreMultipleOpcode()
259 case ARM_AM::da: return ARM::LDMDA; in getLoadStoreMultipleOpcode()
260 case ARM_AM::db: return ARM::LDMDB; in getLoadStoreMultipleOpcode()
261 case ARM_AM::ib: return ARM::LDMIB; in getLoadStoreMultipleOpcode()
[all …]
DARMSelectionDAGInfo.h23 namespace ARM_AM {
26 default: return ARM_AM::no_shift; in getShiftOpcForNode()
27 case ISD::SHL: return ARM_AM::lsl; in getShiftOpcForNode()
28 case ISD::SRL: return ARM_AM::lsr; in getShiftOpcForNode()
29 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
30 case ISD::ROTR: return ARM_AM::ror; in getShiftOpcForNode()
DARMBaseInstrInfo.cpp184 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; in convertToThreeAddress()
185 unsigned Amt = ARM_AM::getAM2Offset(OffImm); in convertToThreeAddress()
187 if (ARM_AM::getSOImmVal(Amt) == -1) in convertToThreeAddress()
198 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); in convertToThreeAddress()
199 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); in convertToThreeAddress()
218 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; in convertToThreeAddress()
219 unsigned Amt = ARM_AM::getAM3Offset(OffImm); in convertToThreeAddress()
584 bool isSub = ARM_AM::getAM3Op(OpcImm) == ARM_AM::sub; in isAddrMode3OpMinusReg()
592 return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift; in isLdstScaledReg()
601 bool isAdd = ARM_AM::getAM2Op(OffImm) == ARM_AM::add; in isLdstScaledRegNotPlusLsl2()
[all …]
DThumb2InstrInfo.cpp257 ARM_AM::getT2SOImmVal(NumBytes) == -1) { in emitT2RegPlusImmediate()
329 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) { in emitT2RegPlusImmediate()
334 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt); in emitT2RegPlusImmediate()
336 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 && in emitT2RegPlusImmediate()
342 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) { in emitT2RegPlusImmediate()
351 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt); in emitT2RegPlusImmediate()
353 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 && in emitT2RegPlusImmediate()
516 if (ARM_AM::getT2SOImmVal(Offset) != -1) { in rewriteT2FrameIndex()
542 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt); in rewriteT2FrameIndex()
547 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 && in rewriteT2FrameIndex()
[all …]
DARMISelDAGToDAG.cpp83 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
155 return ARM_AM::getSOImmVal(Imm) != -1; in is_so_imm()
159 return ARM_AM::getSOImmVal(~Imm) != -1; in is_so_imm_not()
163 return ARM_AM::getT2SOImmVal(Imm) != -1; in is_t2_so_imm()
167 return ARM_AM::getT2SOImmVal(~Imm) != -1; in is_t2_so_imm_not()
440 ARM_AM::ShiftOpc ShOpcVal, in isShifterOpProfitable()
447 return ShOpcVal == ARM_AM::lsl && in isShifterOpProfitable()
455 (Val <= 0xffff || ARM_AM::getT2SOImmValSplatVal(Val) != -1)) in ConstantMaterializationCost()
459 if (ARM_AM::isThumbImmShiftedVal(Val)) return 2; // MOV + LSL in ConstantMaterializationCost()
461 if (ARM_AM::getSOImmVal(Val) != -1) return 1; // MOV in ConstantMaterializationCost()
[all …]
/external/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp207 int Offset = isAM3 ? ARM_AM::getAM3Offset(OffField) in getMemoryOpOffset()
208 : ARM_AM::getAM5Offset(OffField) * 4; in getMemoryOpOffset()
209 ARM_AM::AddrOpc Op = isAM3 ? ARM_AM::getAM3Op(OffField) in getMemoryOpOffset()
210 : ARM_AM::getAM5Op(OffField); in getMemoryOpOffset()
212 if (Op == ARM_AM::sub) in getMemoryOpOffset()
226 static int getLoadStoreMultipleOpcode(unsigned Opcode, ARM_AM::AMSubMode Mode) { in getLoadStoreMultipleOpcode()
233 case ARM_AM::ia: return ARM::LDMIA; in getLoadStoreMultipleOpcode()
234 case ARM_AM::da: return ARM::LDMDA; in getLoadStoreMultipleOpcode()
235 case ARM_AM::db: return ARM::LDMDB; in getLoadStoreMultipleOpcode()
236 case ARM_AM::ib: return ARM::LDMIB; in getLoadStoreMultipleOpcode()
[all …]
DARMSelectionDAGInfo.h23 namespace ARM_AM {
26 default: return ARM_AM::no_shift; in getShiftOpcForNode()
27 case ISD::SHL: return ARM_AM::lsl; in getShiftOpcForNode()
28 case ISD::SRL: return ARM_AM::lsr; in getShiftOpcForNode()
29 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
30 case ISD::ROTR: return ARM_AM::ror; in getShiftOpcForNode()
DARMISelDAGToDAG.cpp89 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
177 return ARM_AM::getSOImmVal(Imm) != -1; in is_so_imm()
181 return ARM_AM::getSOImmVal(~Imm) != -1; in is_so_imm_not()
185 return ARM_AM::getT2SOImmVal(Imm) != -1; in is_t2_so_imm()
189 return ARM_AM::getT2SOImmVal(~Imm) != -1; in is_t2_so_imm_not()
464 ARM_AM::ShiftOpc ShOpcVal, in isShifterOpProfitable()
471 return ShOpcVal == ARM_AM::lsl && in isShifterOpProfitable()
481 if (ARM_AM::isThumbImmShiftedVal(Val)) return 2; // MOV + LSL in ConstantMaterializationCost()
483 if (ARM_AM::getSOImmVal(Val) != -1) return 1; // MOV in ConstantMaterializationCost()
484 if (ARM_AM::getSOImmVal(~Val) != -1) return 1; // MVN in ConstantMaterializationCost()
[all …]
DARMBaseInstrInfo.cpp160 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; in convertToThreeAddress()
161 unsigned Amt = ARM_AM::getAM2Offset(OffImm); in convertToThreeAddress()
163 if (ARM_AM::getSOImmVal(Amt) == -1) in convertToThreeAddress()
175 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); in convertToThreeAddress()
176 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); in convertToThreeAddress()
197 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; in convertToThreeAddress()
198 unsigned Amt = ARM_AM::getAM3Offset(OffImm); in convertToThreeAddress()
2016 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); in emitARMRegPlusImmediate()
2017 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); in emitARMRegPlusImmediate()
2023 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); in emitARMRegPlusImmediate()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp90 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
333 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
343 ARM_AM::ShiftOpc ShiftTy;
352 ARM_AM::ShiftOpc ShiftTy;
358 ARM_AM::ShiftOpc ShiftTy;
643 return ARM_AM::getSOImmVal(Value) != -1; in isARMSOImm()
651 return ARM_AM::getT2SOImmVal(Value) != -1; in isT2SOImm()
675 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift; in isPostIdxReg()
708 if (Memory.ShiftType != ARM_AM::no_shift) return false; in isAddrMode3()
720 return PostIdxReg.ShiftTy == ARM_AM::no_shift; in isAM3Offset()
[all …]
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp204 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
515 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
525 ARM_AM::ShiftOpc ShiftTy;
535 ARM_AM::ShiftOpc ShiftTy;
542 ARM_AM::ShiftOpc ShiftTy;
751 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); in isFPImm()
1022 return (ARM_AM::getSOImmVal(Value) != -1 || in isAdrLabel()
1023 ARM_AM::getSOImmVal(-Value) != -1); in isAdrLabel()
1030 return ARM_AM::getT2SOImmVal(Value) != -1; in isT2SOImm()
1037 return ARM_AM::getT2SOImmVal(Value) == -1 && in isT2SOImmNot()
[all …]

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