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Searched refs:AddrIndexReg (Results 1 – 25 of 29) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp69 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is16BitMemOperand()
211 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is32BitMemOperand()
232 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is64BitMemOperand()
386 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in emitMemModRMByte()
752 unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg); in EmitVEXOpcodePrefix()
797 unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg); in EmitVEXOpcodePrefix()
812 unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg); in EmitVEXOpcodePrefix()
828 unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg); in EmitVEXOpcodePrefix()
850 unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg); in EmitVEXOpcodePrefix()
1069 REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X in DetermineREXPrefix()
[all …]
DX86BaseInfo.h35 AddrIndexReg = 2, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/InstPrinter/
DX86IntelInstPrinter.cpp76 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference()
94 printOperand(MI, Op+X86::AddrIndexReg, O); in printMemReference()
DX86ATTInstPrinter.cpp114 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference()
138 printOperand(MI, Op + X86::AddrIndexReg, O); in printMemReference()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is16BitMemOperand()
207 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is32BitMemOperand()
226 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is64BitMemOperand()
357 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in emitMemModRMByte()
722 unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg); in EmitVEXOpcodePrefix()
768 unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg); in EmitVEXOpcodePrefix()
800 unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg); in EmitVEXOpcodePrefix()
997 REX |= isX86_64ExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X in DetermineREXPrefix()
1007 REX |= isX86_64ExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X in DetermineREXPrefix()
1017 REX |= isX86_64ExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X in DetermineREXPrefix()
DX86BaseInfo.h35 AddrIndexReg = 2, enumerator
/external/llvm/lib/Target/X86/InstPrinter/
DX86IntelInstPrinter.cpp161 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference()
183 printOperand(MI, Op+X86::AddrIndexReg, O); in printMemReference()
DX86ATTInstPrinter.cpp198 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference()
226 printOperand(MI, Op + X86::AddrIndexReg, O); in printMemReference()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86AsmPrinter.cpp260 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printLeaMemReference()
299 printOperand(P, MI, Op+X86::AddrIndexReg, O, Modifier); in printLeaMemReference()
326 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printIntelMemReference()
348 printOperand(P, MI, Op+X86::AddrIndexReg, O, Modifier, AsmVariant); in printIntelMemReference()
DX86FixupLEAs.cpp338 LEA.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && in isLEASimpleIncOrDec()
391 MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg); in processInstruction()
DX86OptimizeLEAs.cpp194 &MI.getOperand(N + X86::AddrIndexReg), in getMemOpKey()
550 MI.getOperand(MemOpNo + X86::AddrIndexReg) in removeRedundantAddrCalc()
DX86SpeculativeLoadHardening.cpp1445 MI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in tracePredStateThroughBlocksAndHarden()
1525 MI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in tracePredStateThroughBlocksAndHarden()
1915 UseMI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in sinkPostLoadHardenedInst()
DX86InstrInfo.h153 MI.getOperand(Op + X86::AddrIndexReg).isReg() && in isLeaMem()
DX86CallFrameOptimization.cpp429 (I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) || in collectCallInfo()
DX86AvoidStoreForwardingBlocks.cpp321 MachineOperand &Index = MI->getOperand(AddrOffset + X86::AddrIndexReg); in isRelevantAddressingMode()
DX86InstrInfo.cpp198 MI.getOperand(Op + X86::AddrIndexReg).isReg() && in isFrameOperand()
201 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 && in isFrameOperand()
541 MI.getOperand(1 + X86::AddrIndexReg).isReg() && in isReallyTriviallyReMaterializable()
542 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && in isReallyTriviallyReMaterializable()
560 MI.getOperand(1 + X86::AddrIndexReg).isReg() && in isReallyTriviallyReMaterializable()
561 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && in isReallyTriviallyReMaterializable()
3263 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() != in getMemOpBaseRegImmOfs()
5795 !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg)) in areLoadsFromSameBasePtr()
DX86MCInstLower.cpp345 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && in SimplifyShortMoveForm()
369 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0)) in SimplifyShortMoveForm()
/external/llvm/lib/Target/X86/
DX86AsmPrinter.cpp232 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printLeaMemReference()
271 printOperand(P, MI, Op+X86::AddrIndexReg, O, Modifier); in printLeaMemReference()
298 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printIntelMemReference()
320 printOperand(P, MI, Op+X86::AddrIndexReg, O, Modifier, AsmVariant); in printIntelMemReference()
DX86FixupLEAs.cpp258 LEA.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && in isLEASimpleIncOrDec()
311 MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg); in processInstruction()
DX86OptimizeLEAs.cpp176 &MI.getOperand(N + X86::AddrIndexReg), in getMemOpKey()
523 MI.getOperand(MemOpNo + X86::AddrIndexReg) in removeRedundantAddrCalc()
DX86InstrInfo.h127 MI.getOperand(Op + X86::AddrIndexReg).isReg() && in isLeaMem()
DX86CallFrameOptimization.cpp389 (I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) || in collectCallInfo()
DX86MCInstLower.cpp315 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && in SimplifyShortMoveForm()
340 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0)) in SimplifyShortMoveForm()
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp163 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is32BitMemOperand()
249 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in EmitMemModRMByte()
507 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg())) in EmitVEXOpcodePrefix()
539 MI.getOperand(MemAddrOffset+X86::AddrIndexReg).getReg())) in EmitVEXOpcodePrefix()
551 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg())) in EmitVEXOpcodePrefix()
DX86BaseInfo.h34 AddrIndexReg = 2, enumerator

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