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Searched refs:AddrReg (Results 1 – 25 of 29) sorted by relevance

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/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsNaClELFStreamer.cpp93 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask() argument
97 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
98 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
106 unsigned AddrReg = MI.getOperand(0).getReg(); in sandboxIndirectJump() local
109 emitMask(AddrReg, IndirectBranchMaskReg, STI); in sandboxIndirectJump()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsNaClELFStreamer.cpp102 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask() argument
106 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
107 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
115 unsigned AddrReg = MI.getOperand(0).getReg(); in sandboxIndirectJump() local
118 emitMask(AddrReg, IndirectBranchMaskReg, STI); in sandboxIndirectJump()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSILoadStoreOptimizer.cpp315 const MachineOperand *AddrReg[3]; in findMatchingInst() local
340 AddrReg[i] = &CI.I->getOperand(AddrIdx[i]); in findMatchingInst()
344 if (AddrReg[i]->isReg() && in findMatchingInst()
345 (TargetRegisterInfo::isPhysicalRegister(AddrReg[i]->getReg()) || in findMatchingInst()
346 MRI->hasOneNonDBGUse(AddrReg[i]->getReg()))) in findMatchingInst()
407 if (AddrReg[i]->isImm() || AddrRegNext.isImm()) { in findMatchingInst()
408 if (AddrReg[i]->isImm() != AddrRegNext.isImm() || in findMatchingInst()
409 AddrReg[i]->getImm() != AddrRegNext.getImm()) { in findMatchingInst()
418 if (AddrReg[i]->getReg() != AddrRegNext.getReg() || in findMatchingInst()
419 AddrReg[i]->getSubReg() != AddrRegNext.getSubReg()) { in findMatchingInst()
[all …]
DR600InstrInfo.cpp1126 unsigned AddrReg; in buildIndirectWrite() local
1129 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break; in buildIndirectWrite()
1130 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectWrite()
1131 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectWrite()
1132 case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address); break; in buildIndirectWrite()
1139 AddrReg, ValueReg) in buildIndirectWrite()
1158 unsigned AddrReg; in buildIndirectRead() local
1161 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break; in buildIndirectRead()
1162 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectRead()
1163 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectRead()
[all …]
DSIInstrInfo.cpp277 const MachineOperand *AddrReg = in getMemOpBaseRegImmOfs() local
280 BaseReg = AddrReg->getReg(); in getMemOpBaseRegImmOfs()
312 const MachineOperand *AddrReg = in getMemOpBaseRegImmOfs() local
314 BaseReg = AddrReg->getReg(); in getMemOpBaseRegImmOfs()
327 const MachineOperand *AddrReg = in getMemOpBaseRegImmOfs() local
329 if (!AddrReg) in getMemOpBaseRegImmOfs()
334 BaseReg = AddrReg->getReg(); in getMemOpBaseRegImmOfs()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/
DARCExpandPseudos.cpp63 unsigned AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in ExpandStore() local
66 BuildMI(*SI.getParent(), SI, SI.getDebugLoc(), TII->get(AddOpc), AddrReg) in ExpandStore()
72 .addReg(AddrReg) in ExpandStore()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64CallLowering.cpp64 unsigned AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 64)); in getStackAddress() local
65 MIRBuilder.buildFrameIndex(AddrReg, FI); in getStackAddress()
67 return AddrReg; in getStackAddress()
142 unsigned AddrReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
143 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg); in getStackAddress()
146 return AddrReg; in getStackAddress()
DAArch64SIMDInstrOpt.cpp505 unsigned SeqReg, AddrReg; in optimizeLdStInterleave() local
519 AddrReg = MI.getOperand(1).getReg(); in optimizeLdStInterleave()
573 .addReg(AddrReg) in optimizeLdStInterleave()
613 .addReg(AddrReg) in optimizeLdStInterleave()
618 .addReg(AddrReg) in optimizeLdStInterleave()
DAArch64ExpandPseudoInsts.cpp601 unsigned AddrReg = MI.getOperand(2).getReg(); in expandCMP_SWAP() local
623 .addReg(AddrReg); in expandCMP_SWAP()
640 .addReg(AddrReg); in expandCMP_SWAP()
681 unsigned AddrReg = MI.getOperand(3).getReg(); in expandCMP_SWAP_128() local
704 .addReg(AddrReg); in expandCMP_SWAP_128()
733 .addReg(AddrReg); in expandCMP_SWAP_128()
DAArch64FastISel.cpp232 bool emitStoreRelease(MVT VT, unsigned SrcReg, unsigned AddrReg,
2055 unsigned AddrReg, in emitStoreRelease() argument
2068 AddrReg = constrainOperandRegClass(II, AddrReg, 1); in emitStoreRelease()
2071 .addReg(AddrReg) in emitStoreRelease()
2195 unsigned AddrReg = getRegForValue(PtrV); in selectStore() local
2196 return emitStoreRelease(VT, SrcReg, AddrReg, in selectStore()
2510 unsigned AddrReg = getRegForValue(BI->getOperand(0)); in selectIndirectBr() local
2511 if (AddrReg == 0) in selectIndirectBr()
2516 AddrReg = constrainOperandRegClass(II, AddrReg, II.getNumDefs()); in selectIndirectBr()
2517 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(AddrReg); in selectIndirectBr()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86CallLowering.cpp119 unsigned AddrReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
120 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg); in getStackAddress()
123 return AddrReg; in getStackAddress()
233 unsigned AddrReg = MRI.createGenericVirtualRegister( in getStackAddress() local
235 MIRBuilder.buildFrameIndex(AddrReg, FI); in getStackAddress()
236 return AddrReg; in getStackAddress()
DX86InstructionSelector.cpp1345 unsigned AddrReg = MRI.createVirtualRegister(&X86::GR64RegClass); in materializeFP() local
1346 BuildMI(*I.getParent(), I, DbgLoc, TII.get(X86::MOV64ri), AddrReg) in materializeFP()
1355 AddrReg) in materializeFP()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsCallLowering.cpp101 unsigned AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32)); in getStackAddress() local
102 MIRBuilder.buildFrameIndex(AddrReg, FI); in getStackAddress()
104 return AddrReg; in getStackAddress()
162 unsigned AddrReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
163 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg); in getStackAddress()
166 return AddrReg; in getStackAddress()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMCallLowering.cpp107 unsigned AddrReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
108 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg); in getStackAddress()
111 return AddrReg; in getStackAddress()
306 unsigned AddrReg = in getStackAddress() local
308 MIRBuilder.buildFrameIndex(AddrReg, FI); in getStackAddress()
310 return AddrReg; in getStackAddress()
DARMExpandPseudoInsts.cpp932 unsigned AddrReg = MI.getOperand(2).getReg(); in ExpandCMP_SWAP() local
961 MIB.addReg(AddrReg); in ExpandCMP_SWAP()
985 .addReg(AddrReg); in ExpandCMP_SWAP()
1051 unsigned AddrReg = MI.getOperand(2).getReg(); in ExpandCMP_SWAP_64() local
1079 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); in ExpandCMP_SWAP_64()
1107 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); in ExpandCMP_SWAP_64()
DARMFastISel.cpp1336 unsigned AddrReg = getRegForValue(I->getOperand(0)); in SelectIndirectBr() local
1337 if (AddrReg == 0) return false; in SelectIndirectBr()
1343 TII.get(Opc)).addReg(AddrReg)); in SelectIndirectBr()
/external/llvm/lib/Target/AMDGPU/
DR600InstrInfo.cpp1145 unsigned AddrReg; in buildIndirectWrite() local
1148 case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break; in buildIndirectWrite()
1149 case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectWrite()
1150 case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectWrite()
1151 case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address); break; in buildIndirectWrite()
1158 AddrReg, ValueReg) in buildIndirectWrite()
1177 unsigned AddrReg; in buildIndirectRead() local
1180 case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break; in buildIndirectRead()
1181 case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectRead()
1182 case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectRead()
[all …]
DSILoadStoreOptimizer.cpp200 const MachineOperand *AddrReg = TII->getNamedOperand(*I, AMDGPU::OpName::addr); in mergeRead2Pair() local
236 .addOperand(*AddrReg) // addr in mergeRead2Pair()
273 LiveInterval &AddrRegLI = LIS->getInterval(AddrReg->getReg()); in mergeRead2Pair()
DSIInstrInfo.cpp215 const MachineOperand *AddrReg = in getMemOpBaseRegImmOfs() local
218 BaseReg = AddrReg->getReg(); in getMemOpBaseRegImmOfs()
250 const MachineOperand *AddrReg = in getMemOpBaseRegImmOfs() local
252 BaseReg = AddrReg->getReg(); in getMemOpBaseRegImmOfs()
264 const MachineOperand *AddrReg = in getMemOpBaseRegImmOfs() local
266 if (!AddrReg) in getMemOpBaseRegImmOfs()
271 BaseReg = AddrReg->getReg(); in getMemOpBaseRegImmOfs()
290 const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::addr); in getMemOpBaseRegImmOfs() local
291 BaseReg = AddrReg->getReg(); in getMemOpBaseRegImmOfs()
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp705 unsigned AddrReg = MI->getOperand(OpNum++).getReg(); in printInst() local
706 O << ", [" << getRegisterName(AddrReg) << ']'; in printInst()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp1767 unsigned AddrReg = getRegForValue(I->getOperand(0)); in SelectIndirectBr() local
1768 if (AddrReg == 0) in SelectIndirectBr()
1772 .addReg(AddrReg); in SelectIndirectBr()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp1854 unsigned AddrReg = getRegForValue(I->getOperand(0)); in SelectIndirectBr() local
1855 if (AddrReg == 0) in SelectIndirectBr()
1859 .addReg(AddrReg); in SelectIndirectBr()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp727 unsigned AddrReg = MI->getOperand(OpNum++).getReg(); in printInst() local
728 O << ", [" << getRegisterName(AddrReg) << ']'; in printInst()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp2421 unsigned AddrReg = getRegForValue(BI->getOperand(0)); in selectIndirectBr() local
2422 if (AddrReg == 0) in selectIndirectBr()
2427 AddrReg = constrainOperandRegClass(II, AddrReg, II.getNumDefs()); in selectIndirectBr()
2428 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(AddrReg); in selectIndirectBr()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp1335 unsigned AddrReg = getRegForValue(I->getOperand(0)); in SelectIndirectBr() local
1336 if (AddrReg == 0) return false; in SelectIndirectBr()
1340 TII.get(Opc)).addReg(AddrReg)); in SelectIndirectBr()

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