| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 122 Opc = Mips::CTC1; in copyPhysReg()
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| D | MipsInstrFPU.td | 175 def CTC1 : FFRGPR<0x6, (outs CCR:$fs), (ins CPURegs:$rt),
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| /external/v8/src/mips/ |
| D | disasm-mips.cc | 673 if ((CTC1 == instr->RsFieldRaw()) || (CFC1 == instr->RsFieldRaw())) { in FormatFPURegister()
1591 case CTC1: in DecodeTypeRegister()
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| D | constants-mips.h | 590 CTC1 = ((0U << 3) + 6) << 21, enumerator
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| D | assembler-mips.cc | 2621 GenInstrRegister(COP1, CTC1, rt, fs); in ctc1()
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| D | simulator-mips.cc | 3680 case CTC1: { in DecodeTypeRegisterCOP1()
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| /external/v8/src/mips64/ |
| D | disasm-mips64.cc | 714 if ((CTC1 == instr->RsFieldRaw()) || (CFC1 == instr->RsFieldRaw())) { in FormatFPURegister()
1379 case CTC1: in DecodeTypeRegisterCOP1()
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| D | constants-mips64.h | 621 CTC1 = ((0U << 3) + 6) << 21, enumerator
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| D | assembler-mips64.cc | 3018 GenInstrRegister(COP1, CTC1, rt, fs); in ctc1()
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| D | simulator-mips64.cc | 3565 case CTC1: { in DecodeTypeRegisterCOP1()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 116 Opc = Mips::CTC1; in copyPhysReg()
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| D | MipsInstrFPU.td | 365 def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 121 Opc = Mips::CTC1; in copyPhysReg()
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| D | MipsScheduleP5600.td | 543 def : InstRW<[P5600WriteMoveGPRToFPU], (instrs CTC1, MTC1, MTC1_D64, MTHC1_D32,
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| D | MipsInstrFPU.td | 485 def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>,
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 463 704592U, // CTC1
2177 0U, // CTC1
4534 // CTC1, CTC1_MM, DAHI, DATI, DMTC1, MTC1, MTC1_MM, MTHC1_MM, MTHI_DSP, M...
4585 // CTC1, CTC1_MM, DMTC1, MTC1, MTC1_MM, MTHC1_MM, MTHI_DSP, MTHLIP, MTLO_...
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| D | MipsGenDisassemblerTables.inc | 823 /* 1677 */ MCD_OPC_Decode, 190, 3, 66, // Opcode: CTC1
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 932 {DBGFIELD("CTC1") 1, false, false, 5, 2, 2, 1, 0, 0}, // #657
1952 {DBGFIELD("CTC1") 2, false, false, 69, 4, 1, 1, 0, 0}, // #657
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| D | MipsGenAsmWriter.inc | 2253 8945789U, // CTC1
4884 0U, // CTC1
6581 // CTTC1, MTTACX, MTTC0, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, CTC1, CTC1_...
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| D | MipsGenMCCodeEmitter.inc | 1038 UINT64_C(1153433600), // CTC1
6471 case Mips::CTC1:
8764 Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CTC1 = 1025
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| D | MipsGenInstrInfo.inc | 1040 CTC1 = 1025,
3314 CTC1 = 657,
5085 …modeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1025 = CTC1
10058 { Mips::CTC1, Mips::CTC1, Mips::CTC1_MM },
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| D | MipsGenDisassemblerTables.inc | 3280 /* 2479 */ MCD::OPC_Decode, 129, 8, 200, 1, // Opcode: CTC1
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| D | MipsGenAsmMatcher.inc | 5861 …{ 2980 /* ctc1 */, Mips::CTC1, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_Is…
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3152 TOut.emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, STI); in expandTrunc()
3157 TOut.emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, STI); in expandTrunc()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4128 TOut.emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, STI); in expandTrunc()
4133 TOut.emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, STI); in expandTrunc()
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