| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoM.td | 25 def DIVU : ALU_rr<0b0000001, 0b101, "divu">;
48 def : PatGprGpr<udiv, DIVU>;
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| /external/v8/src/compiler/mips/ |
| D | instruction-scheduler-mips.cc | 316 DIVU = 50, enumerator
1040 return Latency::DIVU + Latency::MFLO; in DivuLatency()
1042 return Latency::DIVU; in DivuLatency()
1046 return 1 + Latency::DIVU + Latency::MFLO; in DivuLatency()
1048 return 1 + Latency::DIVU; in DivuLatency()
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| /external/v8/src/compiler/mips64/ |
| D | instruction-scheduler-mips64.cc | 346 DIVU = 50, enumerator
558 return Latency::DIVU; in DivuLatency()
560 return Latency::DIVU + 1; in DivuLatency()
608 latency = Latency::DIVU + Latency::MFHI; in ModuLatency()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/ |
| D | Nios2InstrInfo.td | 90 defm DIVU : ArithLogicReg<0x24, "divu", udiv>;
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| /external/v8/src/mips/ |
| D | constants-mips.h | 523 DIVU = ((3U << 3) + 3), enumerator
1288 FunctionFieldToBitNumber(DIV) | FunctionFieldToBitNumber(DIVU) |
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| D | disasm-mips.cc | 1384 case DIVU: // @Mips32r6 == DIV_MOD_U. in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips.cc | 1980 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIVU); in divu()
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| D | simulator-mips.cc | 3957 case DIVU: in DecodeTypeRegisterSPECIAL()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 511 DIVU = ((3U << 3) + 3), enumerator
1332 FunctionFieldToBitNumber(DIVU) | FunctionFieldToBitNumber(DDIVU) |
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| D | disasm-mips64.cc | 1599 case DIVU: // @Mips64r6 == DIV_MOD_U. in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips64.cc | 1997 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIVU); in divu()
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| D | simulator-mips64.cc | 3946 case DIVU: in DecodeTypeRegisterSPECIAL()
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_common.c | 137 #define DIVU (HI(0) | LO(27)) macro
1097 …FAIL_IF(push_inst(compiler, ((op | 0x2) == SLJIT_DIV_UW ? DIVU : DIV) | S(SLJIT_R0) | T(SLJIT_R1),… in sljit_emit_op0()
1101 …FAIL_IF(push_inst(compiler, ((op | 0x2) == SLJIT_DIV_UW ? DIVU : DIV) | S(SLJIT_R0) | T(SLJIT_R1),… in sljit_emit_op0()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Mips64r6InstrInfo.td | 312 (DIVU GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;
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| D | Mips32r6InstrInfo.td | 901 def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
1002 def : MipsInstAlias<"divu $rs, $rt", (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs,
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| D | MipsScheduleP5600.td | 180 def : InstRW<[P5600WriteAL2DivU], (instrs DIVU, PseudoUDIV, UDIV)>;
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| D | Mips16InstrInfo.td | 730 // Format: DIVU rx, ry MIPS16e
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| D | MipsISelLowering.cpp | 1359 case Mips::DIVU: in EmitInstrWithCustomInserter()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips32r6InstrInfo.td | 791 def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
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| D | Mips16InstrInfo.td | 730 // Format: DIVU rx, ry MIPS16e
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| D | MipsISelLowering.cpp | 1048 case Mips::DIVU: in EmitInstrWithCustomInserter()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmWriter.inc | 2415 268459699U, // DIVU
5046 0U, // DIVU
8620 case Mips::DIVU:
8628 // (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt)
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| D | MipsGenMCCodeEmitter.inc | 1200 UINT64_C(155), // DIVU
4418 case Mips::DIVU:
8926 Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // DIVU = 1187
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 565 33577796U, // DIVU
2279 0U, // DIVU
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 2019 case Mips::DIVU: in processInstruction()
|