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Searched refs:DPAU_H_QBL (Results 1 – 18 of 18) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsISelLowering.h127 DPAU_H_QBL, enumerator
DMipsDSPInstrInfo.td55 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
1169 def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
DMipsSEISelLowering.cpp1527 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL); in lowerINTRINSIC_WO_CHAIN()
DMipsISelLowering.cpp168 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; in getTargetNodeName()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsISelLowering.h179 DPAU_H_QBL, enumerator
DMipsDSPInstrInfo.td56 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
1174 def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
DMipsScheduleGeneric.td557 def : InstRW<[GenericDSPShort], (instregex "^DPAU_H_QBL$")>;
DMipsSEISelLowering.cpp1511 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL); in lowerINTRINSIC_WO_CHAIN()
DMipsISelLowering.cpp250 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; in getTargetNodeName()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc1000 {DBGFIELD("DPAU_H_QBL") 1, false, false, 35, 1, 2, 1, 0, 0}, // #725
2020 {DBGFIELD("DPAU_H_QBL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #725
DMipsGenMCCodeEmitter.inc1255 UINT64_C(2080375024), // DPAU_H_QBL
2713 case Mips::DPAU_H_QBL:
8981 Feature_HasDSP | 0, // DPAU_H_QBL = 1242
DMipsGenInstrInfo.inc1257 DPAU_H_QBL = 1242,
3382 DPAU_H_QBL = 725,
5302 … 1, 4, 725, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1242 = DPAU_H_QBL
9749 { Mips::DPAU_H_QBL, Mips::DPAU_H_QBL, Mips::DPAU_H_QBL_MM },
DMipsGenAsmWriter.inc2470 268457964U, // DPAU_H_QBL
5101 0U, // DPAU_H_QBL
DMipsGenDisassemblerTables.inc5937 /* 15887 */ MCD::OPC_Decode, 218, 9, 229, 1, // Opcode: DPAU_H_QBL
DMipsGenDAGISel.inc26494 /* 49809*/ /*SwitchOpcode*/ 29, TARGET_VAL(MipsISD::DPAU_H_QBL),// ->49841
26500 /* 49819*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPAU_H_QBL), 0,
26503 …// Dst: (DPAU_H_QBL:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSP…
DMipsGenAsmMatcher.inc6051 …{ 3598 /* dpau.h.qbl */, Mips::DPAU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg…
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc608 33576321U, // DPAU_H_QBL
2322 0U, // DPAU_H_QBL
DMipsGenDisassemblerTables.inc3405 /* 12327 */ MCD_OPC_Decode, 207, 4, 93, // Opcode: DPAU_H_QBL