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Searched refs:DPSQX_SA_W_PH (Results 1 – 18 of 18) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsISelLowering.h142 DPSQX_SA_W_PH, enumerator
DMipsDSPInstrInfo.td71 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
1260 def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC, ISA_DSPR2;
DMipsSEISelLowering.cpp2234 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH); in lowerINTRINSIC_W_CHAIN()
DMipsISelLowering.cpp183 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; in getTargetNodeName()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsISelLowering.h194 DPSQX_SA_W_PH, enumerator
DMipsDSPInstrInfo.td72 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
1265 def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC, ISA_DSPR2;
DMipsScheduleGeneric.td660 def : InstRW<[GenericDSPShort], (instregex "^DPSQX_SA_W_PH$")>;
DMipsSEISelLowering.cpp2319 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH); in lowerINTRINSIC_W_CHAIN()
DMipsISelLowering.cpp265 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; in getTargetNodeName()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc1099 {DBGFIELD("DPSQX_SA_W_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #824
2119 {DBGFIELD("DPSQX_SA_W_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #824
DMipsGenMCCodeEmitter.inc1264 UINT64_C(2080376560), // DPSQX_SA_W_PH
2717 case Mips::DPSQX_SA_W_PH:
8990 Feature_HasDSPR2 | 0, // DPSQX_SA_W_PH = 1251
DMipsGenInstrInfo.inc1266 DPSQX_SA_W_PH = 1251,
3481 DPSQX_SA_W_PH = 824,
5311 …ts), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1251 = DPSQX_SA_W_PH
9753 { Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH_MMR2 },
DMipsGenAsmWriter.inc2479 268457630U, // DPSQX_SA_W_PH
5110 0U, // DPSQX_SA_W_PH
DMipsGenDisassemblerTables.inc6009 /* 16283 */ MCD::OPC_Decode, 227, 9, 229, 1, // Opcode: DPSQX_SA_W_PH
DMipsGenDAGISel.inc26789 /* 50342*/ /*SwitchOpcode*/ 32, TARGET_VAL(MipsISD::DPSQX_SA_W_PH),// ->50377
26797 /* 50354*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSQX_SA_W_PH), 0|OPFL_Chain,
26800 …// Dst: (DPSQX_SA_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64…
DMipsGenAsmMatcher.inc6067 …{ 3681 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32…
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc613 33576008U, // DPSQX_SA_W_PH
2327 0U, // DPSQX_SA_W_PH
DMipsGenDisassemblerTables.inc3477 /* 12651 */ MCD_OPC_Decode, 212, 4, 93, // Opcode: DPSQX_SA_W_PH