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Searched refs:DPSQX_S_W_PH (Results 1 – 18 of 18) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsISelLowering.h141 DPSQX_S_W_PH, enumerator
DMipsDSPInstrInfo.td70 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
1259 def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC, ISA_DSPR2;
DMipsSEISelLowering.cpp2232 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH); in lowerINTRINSIC_W_CHAIN()
DMipsISelLowering.cpp182 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; in getTargetNodeName()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsISelLowering.h193 DPSQX_S_W_PH, enumerator
DMipsDSPInstrInfo.td71 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
1264 def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC, ISA_DSPR2;
DMipsScheduleGeneric.td659 def : InstRW<[GenericDSPShort], (instregex "^DPSQX_S_W_PH$")>;
DMipsSEISelLowering.cpp2317 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH); in lowerINTRINSIC_W_CHAIN()
DMipsISelLowering.cpp264 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; in getTargetNodeName()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc1098 {DBGFIELD("DPSQX_S_W_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #823
2118 {DBGFIELD("DPSQX_S_W_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #823
DMipsGenMCCodeEmitter.inc1266 UINT64_C(2080376432), // DPSQX_S_W_PH
2718 case Mips::DPSQX_S_W_PH:
8992 Feature_HasDSPR2 | 0, // DPSQX_S_W_PH = 1253
DMipsGenInstrInfo.inc1268 DPSQX_S_W_PH = 1253,
3480 DPSQX_S_W_PH = 823,
5313 …cts), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1253 = DPSQX_S_W_PH
9754 { Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH_MMR2 },
DMipsGenAsmWriter.inc2481 268457712U, // DPSQX_S_W_PH
5112 0U, // DPSQX_S_W_PH
DMipsGenDisassemblerTables.inc6001 /* 16239 */ MCD::OPC_Decode, 229, 9, 229, 1, // Opcode: DPSQX_S_W_PH
DMipsGenDAGISel.inc26769 /* 50307*/ /*SwitchOpcode*/ 32, TARGET_VAL(MipsISD::DPSQX_S_W_PH),// ->50342
26777 /* 50319*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSQX_S_W_PH), 0|OPFL_Chain,
26780 …// Dst: (DPSQX_S_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64D…
DMipsGenAsmMatcher.inc6065 …{ 3668 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32As…
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc614 33576090U, // DPSQX_S_W_PH
2328 0U, // DPSQX_S_W_PH
DMipsGenDisassemblerTables.inc3469 /* 12615 */ MCD_OPC_Decode, 213, 4, 93, // Opcode: DPSQX_S_W_PH