Searched refs:DPSX_W_PH (Results 1 – 18 of 18) sorted by relevance
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 140 DPSX_W_PH, enumerator
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| D | MipsDSPInstrInfo.td | 69 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
1258 def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC, ISA_DSPR2;
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| D | MipsSEISelLowering.cpp | 1541 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH); in lowerINTRINSIC_WO_CHAIN()
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| D | MipsISelLowering.cpp | 181 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; in getTargetNodeName()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 192 DPSX_W_PH, enumerator
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| D | MipsDSPInstrInfo.td | 70 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
1263 def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC, ISA_DSPR2;
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| D | MipsScheduleGeneric.td | 661 def : InstRW<[GenericDSPShort], (instregex "^DPSX_W_PH$")>;
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| D | MipsSEISelLowering.cpp | 1525 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH); in lowerINTRINSIC_WO_CHAIN()
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| D | MipsISelLowering.cpp | 263 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; in getTargetNodeName()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 1100 {DBGFIELD("DPSX_W_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #825
2120 {DBGFIELD("DPSX_W_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #825
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| D | MipsGenMCCodeEmitter.inc | 1282 UINT64_C(2080375408), // DPSX_W_PH
2723 case Mips::DPSX_W_PH:
9008 Feature_HasDSPR2 | 0, // DPSX_W_PH = 1269
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| D | MipsGenInstrInfo.inc | 1284 DPSX_W_PH = 1269,
3482 DPSX_W_PH = 825,
5329 …, 1, 4, 825, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1269 = DPSX_W_PH
9759 { Mips::DPSX_W_PH, Mips::DPSX_W_PH, Mips::DPSX_W_PH_MMR2 },
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| D | MipsGenAsmWriter.inc | 2497 268457747U, // DPSX_W_PH
5128 0U, // DPSX_W_PH
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| D | MipsGenDisassemblerTables.inc | 5961 /* 16019 */ MCD::OPC_Decode, 245, 9, 229, 1, // Opcode: DPSX_W_PH
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| D | MipsGenDAGISel.inc | 26752 /* 50275*/ /*SwitchOpcode*/ 29, TARGET_VAL(MipsISD::DPSX_W_PH),// ->50307
26758 /* 50285*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSX_W_PH), 0,
26761 …// Dst: (DPSX_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPO…
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| D | MipsGenAsmMatcher.inc | 6079 …{ 3777 /* dpsx.w.ph */, Mips::DPSX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_…
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 625 33576125U, // DPSX_W_PH
2339 0U, // DPSX_W_PH
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| D | MipsGenDisassemblerTables.inc | 3429 /* 12435 */ MCD_OPC_Decode, 224, 4, 93, // Opcode: DPSX_W_PH
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