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Searched refs:EXTR_RS_W (Results 1 – 18 of 18) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsISelLowering.h117 EXTR_RS_W, enumerator
DMipsDSPInstrInfo.td44 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
1215 def EXTR_RS_W : DspMMRel, EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1437 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
DMipsSEISelLowering.cpp2204 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W); in lowerINTRINSIC_W_CHAIN()
DMipsISelLowering.cpp160 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; in getTargetNodeName()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsISelLowering.h169 EXTR_RS_W, enumerator
DMipsDSPInstrInfo.td45 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
1220 def EXTR_RS_W : DspMMRel, EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1452 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
DMipsScheduleGeneric.td525 def : InstRW<[GenericDSPLong], (instregex "^EXTR_RS_W$")>;
DMipsSEISelLowering.cpp2289 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W); in lowerINTRINSIC_W_CHAIN()
DMipsISelLowering.cpp242 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; in getTargetNodeName()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc970 {DBGFIELD("EXTR_RS_W") 1, false, false, 35, 1, 13, 1, 0, 0}, // #695
1990 {DBGFIELD("EXTR_RS_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #695
DMipsGenMCCodeEmitter.inc1342 UINT64_C(2080375224), // EXTR_RS_W
5586 case Mips::EXTR_RS_W:
9068 Feature_HasDSP | 0, // EXTR_RS_W = 1329
DMipsGenInstrInfo.inc1344 EXTR_RS_W = 1329,
3352 EXTR_RS_W = 695,
5389 …ffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo225, -1 ,nullptr }, // Inst #1329 = EXTR_RS_W
9769 { Mips::EXTR_RS_W, Mips::EXTR_RS_W, Mips::EXTR_RS_W_MM },
DMipsGenAsmWriter.inc2557 268461041U, // EXTR_RS_W
5188 4U, // EXTR_RS_W
DMipsGenDisassemblerTables.inc6050 /* 16498 */ MCD::OPC_Decode, 177, 10, 197, 2, // Opcode: EXTR_RS_W
DMipsGenDAGISel.inc22261 /* 41165*/ /*SwitchOpcode*/ 39, TARGET_VAL(MipsISD::EXTR_RS_W),// ->41207
22273 /* 41185*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::EXTR_RS_W), 0|OPFL_Chain,
22276 …// Dst: (EXTR_RS_W:{ *:[i32] } ACC64DSP:{ *:[Untyped] }:$ac, (imm:{ *:[i32] })<<P:Predicate_immZEx…
DMipsGenAsmMatcher.inc6177 …{ 3997 /* extr_rs.w */, Mips::EXTR_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5…
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc662 1107320962U, // EXTR_RS_W
2376 0U, // EXTR_RS_W
DMipsGenDisassemblerTables.inc3518 /* 12835 */ MCD_OPC_Decode, 133, 5, 187, 1, // Opcode: EXTR_RS_W