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Searched refs:EXTR_R_W (Results 1 – 18 of 18) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsISelLowering.h116 EXTR_R_W, enumerator
DMipsDSPInstrInfo.td43 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
1213 def EXTR_R_W : DspMMRel, EXTR_R_W_ENC, EXTR_R_W_DESC;
1435 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
DMipsSEISelLowering.cpp2202 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W); in lowerINTRINSIC_W_CHAIN()
DMipsISelLowering.cpp159 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; in getTargetNodeName()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsISelLowering.h168 EXTR_R_W, enumerator
DMipsDSPInstrInfo.td44 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
1218 def EXTR_R_W : DspMMRel, EXTR_R_W_ENC, EXTR_R_W_DESC;
1450 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
DMipsScheduleGeneric.td526 def : InstRW<[GenericDSPLong], (instregex "^EXTR_R_W$")>;
DMipsSEISelLowering.cpp2287 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W); in lowerINTRINSIC_W_CHAIN()
DMipsISelLowering.cpp241 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; in getTargetNodeName()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc971 {DBGFIELD("EXTR_R_W") 1, false, false, 35, 1, 13, 1, 0, 0}, // #696
1991 {DBGFIELD("EXTR_R_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #696
DMipsGenMCCodeEmitter.inc1344 UINT64_C(2080375096), // EXTR_R_W
5587 case Mips::EXTR_R_W:
9070 Feature_HasDSP | 0, // EXTR_R_W = 1331
DMipsGenInstrInfo.inc1346 EXTR_R_W = 1331,
3353 EXTR_R_W = 696,
5391 …Effects), 0x6ULL, nullptr, ImplicitList16, OperandInfo225, -1 ,nullptr }, // Inst #1331 = EXTR_R_W
9770 { Mips::EXTR_R_W, Mips::EXTR_R_W, Mips::EXTR_R_W_MM },
DMipsGenAsmWriter.inc2559 268460585U, // EXTR_R_W
5190 4U, // EXTR_R_W
DMipsGenDisassemblerTables.inc6042 /* 16454 */ MCD::OPC_Decode, 179, 10, 197, 2, // Opcode: EXTR_R_W
DMipsGenDAGISel.inc22236 /* 41123*/ /*SwitchOpcode*/ 39, TARGET_VAL(MipsISD::EXTR_R_W),// ->41165
22248 /* 41143*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::EXTR_R_W), 0|OPFL_Chain,
22251 …// Dst: (EXTR_R_W:{ *:[i32] } ACC64DSP:{ *:[Untyped] }:$ac, (imm:{ *:[i32] })<<P:Predicate_immZExt…
DMipsGenAsmMatcher.inc6175 …{ 3988 /* extr_r.w */, Mips::EXTR_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_0…
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc663 1107320506U, // EXTR_R_W
2377 0U, // EXTR_R_W
DMipsGenDisassemblerTables.inc3510 /* 12797 */ MCD_OPC_Decode, 134, 5, 187, 1, // Opcode: EXTR_R_W