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Searched refs:MAQ_S_W_PHL (Results 1 – 18 of 18) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsISelLowering.h123 MAQ_S_W_PHL, enumerator
DMipsDSPInstrInfo.td50 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
1161 def MAQ_S_W_PHL : DspMMRel, MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
DMipsSEISelLowering.cpp2212 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL); in lowerINTRINSIC_W_CHAIN()
DMipsISelLowering.cpp164 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; in getTargetNodeName()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsISelLowering.h175 MAQ_S_W_PHL, enumerator
DMipsDSPInstrInfo.td51 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
1166 def MAQ_S_W_PHL : DspMMRel, MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
DMipsScheduleGeneric.td574 def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHL$")>;
DMipsSEISelLowering.cpp2297 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL); in lowerINTRINSIC_W_CHAIN()
DMipsISelLowering.cpp246 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; in getTargetNodeName()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc1017 {DBGFIELD("MAQ_S_W_PHL") 1, false, false, 35, 1, 2, 1, 0, 0}, // #742
2037 {DBGFIELD("MAQ_S_W_PHL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #742
DMipsGenMCCodeEmitter.inc1776 UINT64_C(2080376112), // MAQ_S_W_PHL
2729 case Mips::MAQ_S_W_PHL:
9502 Feature_HasDSP | 0, // MAQ_S_W_PHL = 1763
DMipsGenInstrInfo.inc1778 MAQ_S_W_PHL = 1763,
3399 MAQ_S_W_PHL = 742,
5823 …ects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1763 = MAQ_S_W_PHL
9782 { Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL_MM },
DMipsGenAsmWriter.inc2991 268458098U, // MAQ_S_W_PHL
5622 0U, // MAQ_S_W_PHL
DMipsGenDisassemblerTables.inc5989 /* 16173 */ MCD::OPC_Decode, 227, 13, 229, 1, // Opcode: MAQ_S_W_PHL
DMipsGenDAGISel.inc26414 /* 49669*/ /*SwitchOpcode*/ 32, TARGET_VAL(MipsISD::MAQ_S_W_PHL),// ->49704
26422 /* 49681*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAQ_S_W_PHL), 0|OPFL_Chain,
26425 …// Dst: (MAQ_S_W_PHL:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DS…
DMipsGenAsmMatcher.inc6568 …{ 5783 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmR…
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc1028 33576464U, // MAQ_S_W_PHL
2742 0U, // MAQ_S_W_PHL
DMipsGenDisassemblerTables.inc3457 /* 12561 */ MCD_OPC_Decode, 243, 7, 93, // Opcode: MAQ_S_W_PHL