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Searched refs:MAQ_S_W_PHR (Results 1 – 18 of 18) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsISelLowering.h124 MAQ_S_W_PHR, enumerator
DMipsDSPInstrInfo.td51 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
1162 def MAQ_S_W_PHR : DspMMRel, MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
DMipsSEISelLowering.cpp2214 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR); in lowerINTRINSIC_W_CHAIN()
DMipsISelLowering.cpp165 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; in getTargetNodeName()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsISelLowering.h176 MAQ_S_W_PHR, enumerator
DMipsDSPInstrInfo.td52 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
1167 def MAQ_S_W_PHR : DspMMRel, MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
DMipsScheduleGeneric.td575 def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHR$")>;
DMipsSEISelLowering.cpp2299 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR); in lowerINTRINSIC_W_CHAIN()
DMipsISelLowering.cpp247 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; in getTargetNodeName()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc1018 {DBGFIELD("MAQ_S_W_PHR") 1, false, false, 35, 1, 2, 1, 0, 0}, // #743
2038 {DBGFIELD("MAQ_S_W_PHR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #743
DMipsGenMCCodeEmitter.inc1778 UINT64_C(2080376240), // MAQ_S_W_PHR
2730 case Mips::MAQ_S_W_PHR:
9504 Feature_HasDSP | 0, // MAQ_S_W_PHR = 1765
DMipsGenInstrInfo.inc1780 MAQ_S_W_PHR = 1765,
3400 MAQ_S_W_PHR = 743,
5825 …ects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1765 = MAQ_S_W_PHR
9783 { Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR_MM },
DMipsGenAsmWriter.inc2993 268458643U, // MAQ_S_W_PHR
5624 0U, // MAQ_S_W_PHR
DMipsGenDisassemblerTables.inc5993 /* 16195 */ MCD::OPC_Decode, 229, 13, 229, 1, // Opcode: MAQ_S_W_PHR
DMipsGenDAGISel.inc26434 /* 49704*/ /*SwitchOpcode*/ 32, TARGET_VAL(MipsISD::MAQ_S_W_PHR),// ->49739
26442 /* 49716*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAQ_S_W_PHR), 0|OPFL_Chain,
26445 …// Dst: (MAQ_S_W_PHR:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DS…
DMipsGenAsmMatcher.inc6570 …{ 5795 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmR…
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc1029 33576888U, // MAQ_S_W_PHR
2743 0U, // MAQ_S_W_PHR
DMipsGenDisassemblerTables.inc3461 /* 12579 */ MCD_OPC_Decode, 244, 7, 93, // Opcode: MAQ_S_W_PHR