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Searched refs:MTC1_D64 (Results 1 – 12 of 12) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsInstrFPU.td55 def MipsMTC1_D64 : SDNode<"MipsISD::MTC1_D64", SDT_MipsMTC1_D64>;
496 def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>,
872 (MTC1_D64 GPR32Opnd:$src)>, ISA_MIPS1, FGR_64;
DMipsISelLowering.h109 MTC1_D64, enumerator
DMipsScheduleP5600.td543 def : InstRW<[P5600WriteMoveGPRToFPU], (instrs CTC1, MTC1, MTC1_D64, MTHC1_D32,
DMipsSEISelLowering.cpp413 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0)); in lowerSELECT()
3754 : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1); in emitFPEXTEND_PSEUDO()
DMipsISelLowering.cpp204 case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64"; in getTargetNodeName()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenFastISel.inc949 // FastEmit functions for MipsISD::MTC1_D64.
955 return fastEmitInst_r(Mips::MTC1_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
1208 case MipsISD::MTC1_D64: return fastEmit_MipsISD_MTC1_D64_r(VT, RetVT, Op0, Op0IsKill);
DMipsGenMCCodeEmitter.inc1954 UINT64_C(1149239296), // MTC1_D64
6474 case Mips::MTC1_D64: {
9680 …tdEnc | Feature_IsFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MTC1_D64 = 1941
DMipsGenAsmWriter.inc3169 8945796U, // MTC1_D64
5800 0U, // MTC1_D64
DMipsGenInstrInfo.inc1956 MTC1_D64 = 1941,
6001 …<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1941 = MTC1_D64
DMipsGenDisassemblerTables.inc7083 /* 80 */ MCD::OPC_Decode, 149, 15, 247, 2, // Opcode: MTC1_D64
DMipsGenDAGISel.inc28249 /* 53074*/ /*SwitchOpcode*/ 10, TARGET_VAL(MipsISD::MTC1_D64),// ->53087
28252 /* 53080*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MTC1_D64), 0,
28255 // Dst: (MTC1_D64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
DMipsGenAsmMatcher.inc6774 …{ 6657 /* mtc1 */, Mips::MTC1_D64, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feat…