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Searched refs:OpSize16 (Results 1 – 25 of 29) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86InstrSystem.td79 "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>, OpSize16;
89 "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize16;
99 "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize16;
109 "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize16;
171 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
178 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16;
185 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
192 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize16;
207 OpSize16;
210 OpSize16;
[all …]
DX86InstrControl.td32 [], IIC_RET>, OpSize16;
43 [], IIC_RET_IMM>, OpSize16;
49 "{l}ret{w|f}", [], IIC_RET>, OpSize16;
55 "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize16;
61 OpSize16;
77 "jmp\t$dst", [], IIC_JMP_REL>, OpSize16;
90 [], IIC_Jcc>, OpSize16, TB;
137 OpSize16, Sched<[WriteJump]>;
140 Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>;
160 IIC_JMP_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
[all …]
DX86InstrShiftRotate.td25 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize16;
42 OpSize16;
60 "shl{w}\t$dst", [], IIC_SR>, OpSize16;
79 OpSize16;
95 IIC_SR>, OpSize16;
113 IIC_SR>, OpSize16;
131 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize16;
146 IIC_SR>, OpSize16;
161 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize16;
179 OpSize16;
[all …]
DX86InstrExtension.td17 "{cbtw|cbw}", [], IIC_CBW>, OpSize16; // AX = signext(AL)
24 "{cwtd|cwd}", [], IIC_CBW>, OpSize16; // DX:AX = signext(AX)
45 TB, OpSize16, Sched<[WriteALU]>;
49 TB, OpSize16, Sched<[WriteALULd]>;
71 TB, OpSize16, Sched<[WriteALU]>;
75 TB, OpSize16, Sched<[WriteALULd]>;
DX86InstrInfo.td1062 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
1095 IIC_POP_REG16>, OpSize16;
1099 IIC_POP_REG>, OpSize16;
1101 IIC_POP_MEM>, OpSize16;
1110 IIC_PUSH_REG>, OpSize16;
1114 IIC_PUSH_REG>, OpSize16;
1119 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16;
1121 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16;
1133 IIC_PUSH_MEM>, OpSize16;
1169 OpSize16;
[all …]
DX86InstrArithmetic.td21 "lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, OpSize16;
71 [], IIC_MUL16_REG>, OpSize16, Sched<[WriteIMul]>;
98 [], IIC_MUL16_MEM>, OpSize16, SchedLoadReg<WriteIMulLd>;
118 IIC_IMUL16_RR>, OpSize16, Sched<[WriteIMul]>;
136 "imul{w}\t$src", [], IIC_IMUL16_MEM>, OpSize16,
161 TB, OpSize16;
183 TB, OpSize16;
212 IIC_IMUL16_RRI>, OpSize16;
218 IIC_IMUL16_RRI>, OpSize16;
253 OpSize16;
[all …]
DX86InstrCMovSetCC.td25 IIC_CMOV16_RR>, TB, OpSize16;
47 TB, OpSize16;
DX86InstrTSX.td28 "xbegin\t$dst", []>, OpSize16, Requires<[HasRTM]>;
DX86InstrCompiler.td387 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
399 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
417 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
432 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
612 IIC_ALU_NONMEM>, OpSize16, LOCK;
644 IIC_ALU_MEM>, OpSize16, LOCK;
668 IIC_ALU_MEM>, OpSize16, LOCK;
707 IIC_UNARY_MEM>, OpSize16, LOCK;
744 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK;
837 itin>, OpSize16;
DX86InstrFormats.td150 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
164 class OpSize16 { OperandSize OpSize = OpSize16; }
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrControl.td29 "ret{w}", []>, OpSize16;
35 "ret{w}\t$amt", []>, OpSize16;
41 "{l}ret{w|f}", []>, OpSize16;
47 "{l}ret{w|f}\t$amt", []>, OpSize16;
53 OpSize16;
67 "jmp\t$dst", []>, OpSize16;
80 []>, OpSize16, TB;
125 OpSize16, Sched<[WriteJump]>;
128 OpSize16, Sched<[WriteJumpLd]>;
148 OpSize16, Sched<[WriteJump]>, NOTRACK;
[all …]
DX86InstrShiftRotate.td25 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize16;
42 OpSize16;
59 "shl{w}\t$dst", []>, OpSize16;
78 OpSize16;
94 OpSize16;
111 OpSize16;
129 [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize16;
144 OpSize16;
159 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize16;
177 OpSize16;
[all …]
DX86InstrSystem.td75 OpSize16;
85 "in{w}\t{$port, %ax|ax, $port}", []>, OpSize16;
94 OpSize16;
104 "out{w}\t{%ax, $port|$port, ax}", []>, OpSize16;
167 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
177 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
197 OpSize16, NotMemoryFoldable;
200 OpSize16, NotMemoryFoldable;
221 OpSize16, NotMemoryFoldable;
224 OpSize16, NotMemoryFoldable;
[all …]
DX86InstrExtension.td17 "{cbtw|cbw}", []>, OpSize16, Sched<[WriteALU]>;
24 "{cwtd|cwd}", []>, OpSize16, Sched<[WriteALU]>;
43 TB, OpSize16, Sched<[WriteALU]>;
47 TB, OpSize16, Sched<[WriteALULd]>;
69 TB, OpSize16, Sched<[WriteALU]>;
73 TB, OpSize16, Sched<[WriteALULd]>;
98 []>, TB, OpSize16, Sched<[WriteALU]>, NotMemoryFoldable;
101 []>, TB, OpSize16, Sched<[WriteALU]>, NotMemoryFoldable;
105 []>, OpSize16, TB, Sched<[WriteALULd]>, NotMemoryFoldable;
108 []>, TB, OpSize16, Sched<[WriteALULd]>, NotMemoryFoldable;
DX86InstrInfo.td1159 "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable;
1167 "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable;
1202 OpSize16;
1208 OpSize16, NotMemoryFoldable;
1215 OpSize16;
1222 OpSize16;
1228 OpSize16, NotMemoryFoldable;
1234 "push{w}\t$imm", []>, OpSize16;
1236 "push{w}\t$imm", []>, OpSize16;
1248 OpSize16;
[all …]
DX86InstrArithmetic.td21 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize16;
71 []>, OpSize16, Sched<[WriteIMul]>;
97 "mul{w}\t$src", []>, OpSize16, SchedLoadReg<WriteIMul.Folded>;
117 OpSize16, Sched<[WriteIMul]>;
135 "imul{w}\t$src", []>, OpSize16, SchedLoadReg<WriteIMul.Folded>;
159 Sched<[WriteIMul]>, TB, OpSize16;
179 Sched<[WriteIMul.Folded, ReadAfterLd]>, TB, OpSize16;
204 Sched<[WriteIMul]>, OpSize16;
210 Sched<[WriteIMul]>, OpSize16;
242 Sched<[WriteIMul.Folded]>, OpSize16;
[all …]
DX86InstrCMovSetCC.td26 TB, OpSize16;
46 CondNode, EFLAGS))]>, TB, OpSize16;
DX86InstrTSX.td30 "xbegin\t$dst", []>, OpSize16;
DX86InstrCompiler.td403 [(X86rep_movs i16)]>, REP, OpSize16,
415 [(X86rep_movs i16)]>, REP, OpSize16,
433 [(X86rep_stos i16)]>, REP, OpSize16,
448 [(X86rep_stos i16)]>, REP, OpSize16,
628 OpSize16, LOCK;
658 OpSize16, LOCK;
682 OpSize16, LOCK;
720 OpSize16, LOCK;
777 [(frag addr:$ptr, GR16:$swap, 2)]>, TB, OpSize16, LOCK;
862 OpSize16;
DX86InstrFormats.td167 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
181 class OpSize16 { OperandSize OpSize = OpSize16; }
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp131 OpSize16 = 1, OpSize32 = 2 enumerator
419 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) in insnContext()
423 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) in insnContext()
425 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) in insnContext()
427 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) in insnContext()
429 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) in insnContext()
446 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) in insnContext()
448 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) in insnContext()
450 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) in insnContext()
452 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) in insnContext()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DX86RecognizableInstr.cpp304 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) in insnContext()
308 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) in insnContext()
310 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) in insnContext()
314 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) in insnContext()
316 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) in insnContext()
333 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) in insnContext()
335 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) in insnContext()
343 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) in insnContext()
345 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) in insnContext()
803 if(OpSize == X86Local::OpSize16) { in typeFromString()
[all …]
DX86RecognizableInstr.h137 OpSize16 = 1, OpSize32 = 2 enumerator
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h333 OpSize16 = 1 << OpSizeShift, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h377 OpSize16 = 1 << OpSizeShift, enumerator

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